Scalable parallel test bus and testing method

Details Scalable parallel test bus and testing method Scalable parallel test bus and testing method

1999-05-05

2002-07-16

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06421810

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to test circuits. In particular, the invention relates to test circuits for testing integrated circuits (ICs), IC boards, and IC systems that employ multiple similar functional circuit blocks.
2. Description of the Related Art
Many electronic integrated circuits (ICs), IC boards, and IC systems employ multiple similar circuit blocks. Similar circuit blocks may be defined as circuit blocks that are deterministic; that is, they are each designed to produce, within the same timing window, the same set of outputs when all the circuit blocks receive the same inputs. Often similar circuit blocks are identical, that is, they consist of the exact same circuit elements connected in exactly the same way. In order to verify that the circuit blocks are working as required, some sort of testing procedure is required during the manufacturing process. These circuit blocks can be tested either serially or concurrently. Serial testing works well for defect detection and isolation, but can significantly increase test time. Concurrent testing also works well for defect detection and isolation, but requires a larger number of external control and monitor signals (e.g., latched register bits).
Testing with latched register bits operates as follows. First, the register bits are cleared and the test pattern is started. Next, any error(s) in the pattern set the appropriate bit(s). Normally the bits cannot be cleared except by a hardware reset or the start of a new test pattern. Then, the test pattern ends. Finally, the register bits are read to determine their pass/fail status.
Register bits thus have two disadvantages. First, the test pattern must read a register to determine its pass/fail status, taking additional time. Second, there is no information on the location or nature of the failure, only a binary pass/fail indication.
Thus, there is a need for a test circuit for defect detection and isolation that has a reduced test time as compared to serial testing and a reduced number of external control and monitor signals (or register bits) as compared to concurrent testing.
SUMMARY OF THE INVENTION
The present invention addresses these and other problems of the prior art with an apparatus for and method of testing similar circuit blocks with test signals.
According to one embodiment, an apparatus includes a test circuit and has a first plurality of logic bus circuits, a second plurality of logic bus circuits, and a plurality of selector circuits. Each of the first plurality of logic bus circuits is configured to receive a plurality of input signals corresponding to both a plurality of similar circuit blocks and a respective test signal, and to receive a plurality of select signals corresponding to the plurality of similar circuit blocks, and in accordance therewith generate a plurality of intermediate output signals. The second plurality of logic bus circuits is coupled to the first plurality of logic bus circuits. Each of the second plurality of logic bus circuits is configured to receive a corresponding set of the plurality of intermediate output signals, and in accordance therewith generate a respective test output signal. The plurality of selector circuits is coupled to the first and second pluralities of logic bus circuits. Each of the plurality of selector circuits is configured to receive the corresponding set of the plurality of intermediate output signals and the respective test output signal, and in accordance therewith generate a final output. The final output corresponds to either the respective test output signal or a high-impedance circuit state indicative of an error. The plurality of select signals selectively designate which of the plurality of input signals that the first logic bus circuit uses to generate the plurality of intermediate output signals.
According to another embodiment, a method includes the steps of generating a plurality of test signals; generating, with a plurality of similar circuit blocks, a plurality of input signals corresponding to both the plurality of similar circuit blocks and the plurality of test signals; and receiving the plurality of input signals as a result of the step of generating the plurality of input signals. The method further includes the steps of generating a plurality of select signals corresponding to the plurality of similar circuit blocks, wherein the plurality of select signals selectively designate at least one of the plurality of input signals; generating a plurality of intermediate output signals, in accordance with the step of receiving and the step of generating the plurality of select signals; and generating a plurality of test output signals, in accordance with the step of generating the plurality of intermediate output signals. The method finally includes the step of generating a plurality of final outputs, in accordance with the step of generating the plurality of intermediate output signals and the step of generating the plurality of test output signals, wherein each of the plurality of final outputs corresponds to either one of the plurality of test output signals or a high-impedance circuit state indicative of an error, and wherein the number of the plurality of final outputs corresponds, independently of the number of the plurality of similar circuit blocks, to the number of the plurality of test signals.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth illustrative embodiments in which the principles of the invention are utilized.


REFERENCES:
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patent: 6006343 (1999-12-01), Whetsel
patent: 6049901 (2000-04-01), Stock et al.
patent: 6078540 (2000-06-01), Keeth
Matsuda et al, “A New Array Architecture For Parallel Testing in VLSI Memories,” IEEE, 1989, pp. 322-326.*
Lee Whetsel, “Addressable Test Ports An Approach to Testing Embedded Cores,” IEEE, Sep. 1999.

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