Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-08-28
2009-08-04
Levin, Naum B (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C714S726000, C714S727000, C714S728000, C714S729000, C714S730000, C714S731000
Reexamination Certificate
active
07571402
ABSTRACT:
A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.
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Aloul, Padi A., et al., “Robust SAT-Based Search Algorithm for Leakage Power Reduction”, International Workshop on Power and Timing Modeling, Optimization and Simulation, Seville, Spain, 2002.
Jorgenson Lisa K.
Levin Naum B
Munck William A.
STMicroelectronics Inc.
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