Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-12-06
2005-12-06
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06973631
ABSTRACT:
A computer implemented process of inserting enhanced scan bypass in relation to a bypassed block in an integrated circuit design comprising: receiving an HDL description of the circuit design; wherein the HDL description includes a port specification HDL instruction that specifies port properties of a bypassed block; wherein the HDL description includes an enhanced bypass HDL instruction that specifies how many scan cells to provide per port of the bypassed block in a scan bypass circuit that bypasses the bypassed block; wherein the bypass HDL instruction includes a user-selectable option of at least zero or one or two scan cells per port; in response to the specification HDL instruction and the enhanced bypass HDL instruction, automatically generating a netlist portion that includes scan a bypass circuit that bypasses the bypassed block and that includes the specified number of scan cells per port.
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“Scan Testability Guidelines”, Atmel, Rev. 1312A-12/99, pp. 15-21.
Chen Ihao
Huang Steve C.
Dinh Paul
Incentia Design Systems Corp.
Morrison & Foerster / LLP
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