Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-11-10
2001-08-14
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06275975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer chip architectures, and more particularly to an on-chip data transfer network that includes a scalable mesh architecture with re-configurable paths, which incorporates a configuration manager, for improved information routing between multiple on-chip modules.
2. Description of the Related Art
Computer systems have traditionally comprised a system unit or housing which comprises a plurality of electrical components comprising the computer system. A computer system typically includes a motherboard, which is configured to hold the microprocessor and memory, and the one or more busses used in the computer system. The motherboard typically comprises a plurality of computer chips or electrical components including intelligent peripheral devices, bus controllers, processors, bus bridges, etc.
More recently, computer systems are evolving toward an integration of functions into a handful of computer chips. This coincides with the ability of chip makers to place an increasingly large number of transistors on a single chip. For example, currently chip manufacturers are able to place up to ten million transistors on a single integrated circuit or monolithic substrate. It is anticipated that within several years chip makers will be able to place one billion transistors on a single chip. Thus, computer systems are involving toward comprising a handful of computer chips, where each computer chip comprises a plurality of functions. The integration of a plurality of modules or functions on a single computer chip requires an improved data transfer chip architecture. Also, due to the shorter distances and tighter integration of components on a chip, new data transfer architectures are necessary to take advantage of this environment. Therefore, an improved system and method is desired for including a plurality of different functions or modules on a single computer chip while providing efficient data transfers.
SUMMARY OF THE INVENTION
The present invention comprises a computer chip including a data transfer network. The data transfer network comprises a scalable mesh of a plurality of communications links for transmitting data, a plurality of communication nodes, a plurality of modules, and a network configuration manager. Each of the communication nodes are directly connected to two or more other communication nodes through respective ones of the plurality of communications links. Each of the communication nodes is operable to communicate data over the plurality of communications links in a multiplicity of routes. Each of the plurality of modules is coupled to at least one of the plurality of communication nodes, and the plurality of modules are operable to communicate with each other through the communication nodes. The plurality of communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the plurality of communications links.
In one embodiment, the network configuration manager receives at least one clock signal. The network configuration manager is operable to selectively reconfigure the multiplicity of routes among the plurality of communications links on a clocking basis based on the clock signal. In another embodiment, the network configuration manager is operable to selectively reconfigure the multiplicity of routes among the plurality of communications links on a messaging basis. One or more of the modules are operable to communicate a reconfiguration message to the network configuration manager. The reconfiguration message includes communications link configuration information. The network configuration manager receives the reconfiguration message and reconfigures one or more of the multiplicity of routes among the plurality of communications links based on the communications link configuration information comprised in the reconfiguration message.
In yet another embodiment, the network configuration manager is operable to selectively reconfigure the multiplicity of routes among the plurality of communications links on a process basis. A plurality of the modules are operable to execute a process which requires a first communications link configuration. One or more of the plurality of the modules communicates a reconfiguration message to the network configuration manager and requests the first transfer path configuration information. The network configuration manager receives the reconfiguration message and configures one or more of the plurality of communications links based on the first transfer path configuration information comprised in the reconfiguration message. Any number of pluralities of modules may request a different communications link configuration.
In still another embodiment, the network configuration manager is operable to selectively reconfigure the multiplicity of routes among the plurality of communications links on a process basis. One or more of the modules is operable to execute a process under control of an operating system. The operating system is operable to communicate a reconfiguration message to the network configuration manager, including communications link configuration information. The network configuration manager receives the reconfiguration message and reconfigures one or more of the plurality of communications links based on the communications link configuration information comprised in the reconfiguration message. In various embodiments, the network configuration manager selectively reconfigures one or more of the multiplicity of routes among the plurality of communications links only when commanded to reconfigure, such as by a module or an operating system.
REFERENCES:
patent: 4797882 (1989-01-01), Maxemchuk
patent: 4825206 (1989-04-01), Brice, Jr. et al.
patent: 4933933 (1990-06-01), Dally et al.
patent: 5041963 (1991-08-01), Ebersole et al.
patent: 5138615 (1992-08-01), Lamport et al.
patent: 5153876 (1992-10-01), Sin
patent: 5577213 (1996-11-01), Avery et al.
patent: 5621726 (1997-04-01), Murakimi
patent: 5761516 (1998-06-01), Rostoker et al.
patent: 5908468 (1999-06-01), Hartmann
patent: 5935232 (1999-08-01), Lambrecht et al.
Godfrey Gary Michael
Hartmann Alfred C.
Lambrecht J. Andrew
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Hood Jeffrey C.
Smith Matthew
Speight Jibreel
LandOfFree
Scalable mesh architecture with reconfigurable paths for an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Scalable mesh architecture with reconfigurable paths for an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Scalable mesh architecture with reconfigurable paths for an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2526618