Scalable logic self-test configuration for multiple chips

Details Scalable logic self-test configuration for multiple chips Scalable logic self-test configuration for multiple chips

2006-12-05

2006-12-05

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07146587

ABSTRACT:
A scalable LBIST control structure provides for testing of multiple independent clock domains within a chip and/or across multiple chips. The LBIST control structure sequences all clock domains through each step of the LBIST sequence synchronously, allowing multiple clock domains and/or multiple chips to be controlled from a common point.

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