Scan compression circuit and method of design therefor

Details Scan compression circuit and method of design therefor Scan compression circuit and method of design therefor

2007-05-25

2010-10-12

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07814444

ABSTRACT:
A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.

REFERENCES:
patent: 6300885 (2001-10-01), Davenport et al.
patent: 6829740 (2004-12-01), Rajski et al.
patent: 6993694 (2006-01-01), Kapur et al.
patent: 7159161 (2007-01-01), Lee et al.
patent: 7395473 (2008-07-01), Cheng et al.
patent: 7415678 (2008-08-01), Gizdarski
patent: 2004/0268181 (2004-12-01), Wang et al.
patent: 2005/0268190 (2005-12-01), Kapur et al.
patent: 2006/0064614 (2006-03-01), Abdel-Hafez et al.
Rajski J. et al. “Convolutional Compaction of Test Responses”, International Test Conference, 2003, pp. 745-754.
Wohl, P. et al. “X-Tolerant Compression and Application of Scan ATPG patterns in a BIST architecture”, Proc. of International Test Conference, 2003, pp. 727-736.
Wohl, P. et al. “Minimizing the Impact of Scan Compression”, VLSI Test Symposium, 2007, pp. 8.
Wohl, P. et al. “Design of Compactors for Signature-Analyzers in Built-In Self-Test”, Proceedings of the IEEE International Test Conference, 2001, pp. 10.
Pandey, A.R. et al. “An Incremental Algorithm for Test Generation in Illinois Scan Architecture Based Designs”, Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (Date'02), pp. 8.
Lee, K-J. et al. “Broadcasting Test Patterns to Multiple Circuits”, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, vol. 18, No. 12, Dec. 1999, pp. 1793-1802.
Hetherington, G. et al. “Logic for Large Industrial Designs: Real Issues and Case Studies”, International Test Conference, 1999, pp. 358-367.
Barnhart, C. et al. “OPMISR: The Foundation for Compressed ATPG Vectors”, International Test Conference, 2001, pp. 748-757.
Hamzaoglu, I. et al. “Reducing test application time for full scan embedded cores”, Dig. Papers, 29thInt. Symp. Fault-Tolerant Computing, 1999, pp. 8.
Hsu, F.F. et al. “A Case Study on the Implementation of the Illinois Scan”, International Test Conference, 2001, pp. 538-547.
Krishna, C.V. et al. “Adjustable Width Linear Combinational Scan Vector Decompression”, International Conference on CAD, 2003, pp. 863-866.
Mitra, S. et al. “X-Compact an Efficient Response Compaction Technique for Test Cost Reduction”, International Test Conference, 2002, pp. 311-320.
Mitra, S. et al. “X-tolerant Signature Analysis”, International Test Conference, 2004, pp. 432-441.
Wohl, P. et al. “Analysis and Design of Optimal Combinational Compactors”, VLSI Test Symposium, 2003, pp. 6.
Patel, J.H. et al. “Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns”, VLSI Test Symposium, 2003, pp. 107-112.
Lumetta, S.S. et al. “X-Codes: Theory and Applications of Unknowable Inputs”, UIUC Center for Reliable and High-Performance Computing Technical Report CRHC-03-08, Aug. 2003, pp. 21.
Sharma, M. et al. “X-filter: Filtering unknowns from compacted test responses”, International Test Conference, 2005, pp. 9.
Rajski J. et al. “Synthesis of X-Tolerant Convolutional Compactors”, VLSI Test Symposium, 2005, pp. 6.
Ramnath, S. et al. “Test-model based hierarchical DFT synthesis”, ICCAD IEEE/ACM International Conference, 2002, pp. 286-293.
Wu, D.M. et al. “H-DFT: A Hybrid DFT Architecture for Low-Cost High-Quality Structural Testing”, International Test Conference, 2003, pp. 1229-1238.
Wohl, P. et al. “Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture”, Design Automation Conference, 2003, pp. 566-569.
Rajski, J. et al. “Embedded Deterministic Test for Low Cost Manufacturing Test”, International Test Conference, 2002, pp. 301-310.
Wohl, P. et al. “Effective Diagnostics through Interval Unloads in a BIST Environment”, Design Automation Conference, 2002, pp. 249-254.
Entire Prosecution History of U.S. Appl. No. 11/786,968, filed Apr. 13, 2007 by Peter Wohl et al.

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