Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-12-30
2002-07-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C702S058000, C702S109000, C702S118000, C703S002000, C703S014000
Reexamination Certificate
active
06425111
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of the Invention
The invention relates to the field of modeling field-effect transistors.
2. Prior Art
There is a growing need to provide optimal designs for integrated circuits particularly as the critical dimensions decrease and speed of such circuits increase.
A relatively recent development in mathematics has provided an improved computerated tool for designing integrated circuits using geometric programs. In general, an operating model is developed in the form of a posynomial function. The geometric program once in the form of a convex program can be solved with efficient interior-point methods. The most important feature of geometric programs is that they can be globally solved with great efficiency. The algorithm determines whether the problem is infeasible (i.e., no design can meet all constraints). Also, the starting point of an optimization algorithm does not have any affect on the solution.
One interior-point method is described by K. O. Kortanek, X. Xu, and Y. Ye, “An Infeasible Interior-point Algorithm for Solving Primal and Dual Geometric Programs,” MathProgramming, 76:155-181, 1996. This method has the desirable feature of exploiting sparsity in the problem, (i.e., efficiently handling problems in which each variable appears in only a few constraints). Additional methods of solving geometric programs are described in: Y. Nesterov and A. Nemirovsky, “Interior-Point Polynomial Methods in Convex Programming,” Volume 13 of
Studies in Applied Mathematics,
SIAM, Philadelphia, Pa., 1994; and A. Fiacco and G. McCormick,
NonlinearProgramming: Sequential Unconstrained Minimization Technologies,
Wiley 1968 (Reprinted in SIAM Classics in Applied Mathematics series 1990).
The present invention is directed towards obtaining a posynomial expression for field-effect transistor model when operating in its saturation region. While numerous techniques are well known for obtaining mathematical expressions representing transistor characteristics including the operation of a transistor in its saturation region, these approaches do not necessarily lead to a posynomial expression useful in a geometric program.
The use of posynomial and monomial expression for circuits and their solution with geometric programs is discussed in Ser. No. 09/123,129, filed Jul. 27, 1998, entitled “System and Method for Designing Integrated Circuits,” now U.S. Pat. No. 6,269,277 and Ser. No. 09/335,227, filed Jun. 17, 1999, entitled “Optimal Design of an Inductor and Inductor Circuit”; now U.S. Pat. No. 6,311,145, both assigned to the assignee of this application.
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Blakely , Sokoloff, Taylor & Zafman LLP
Kik Phallaka
Smith Matthew
The Board of Trustees of the Leland Stanford Junior University
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