ESD design, verification and checking system and method of use
Estimating capacitance effects in integrated circuits using...
Estimating capacitances using information including feature...
Estimating current density parameters on signal leads of an...
Estimating free space in IC chips
Estimating LUT power usage
Estimating quality during early synthesis
Estimating the difficulty level of a formal verification...
Evaluating a validation vector for validating a network design
Evaluation device and circuit design method used for the same
Evaluation device and circuit design method used for the same
Evaluation method of semiconductor device, manufacturing...
Evaluation of a technology library for use in an electronic...
Evaluation of the design quality of network nodes
Evaluation TEG for semiconductor device and method of...
Evaluation TEG for semiconductor device and method of...
Event-based temporal logic
Evolutionary programming of configurable logic devices
Evolutionary technique for automated synthesis of electronic...
Exploiting suspected redundancy for enhanced design...