Estimating capacitances using information including feature...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07036096

ABSTRACT:
The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool (120) to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element (130) aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (140), which uses the total capacitance of each input or output to generate a timing model for the circuit.

REFERENCES:
patent: 6550050 (2003-04-01), Hosono et al.

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