Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-11-07
2006-11-07
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07134099
ABSTRACT:
A computerized method and system for designing, verification and checking of the electrostatic discharge (ESD) protection circuits and their implementation in a integrated computer chip design where the computer chip comprises of electronic circuits designed in a parameterized cell design system, pads, interconnects and the ESD system uses a hierarchical system of parameterized cells (p-cells) which are constructed into higher level ESD networks. Lowest order p-cells pass user defined parameters to higher order p-cells to form an ESD protection circuit meeting design criteria. Ones of the p-cells are “grow-able” such that they can form repetition groups of the underlying p-cell element to accommodate the design parameters. Layout and circuit schematics are auto-generated with the user varying the number of elements in the circuit by adjusting the input parameters. The circuit topology automation allows for the customer to auto generate new ESD circuits and ESD power clamps without additional design work.
REFERENCES:
patent: 6466423 (2002-10-01), Yu
patent: 6502229 (2002-12-01), Lee et al.
patent: 6594809 (2003-07-01), Wang et al.
patent: 6704179 (2004-03-01), Voldman
patent: 6862723 (2005-03-01), Wang et al.
patent: 2004/0225985 (2004-11-01), Kashiwagi et al.
Sue E. Strang, et al., “A Design System for Auto-Generation of ESD Circuits”, International Cadence Usergroup Conference, Sep. 16-18, 2002, San Jose, California.
Collins David S.
Jordan Donald L.
Strang Sue E.
Voldman Steven H.
Dinh Paul
Greenblum & Bernstein P.L.C.
Kotulak, Esq. Richard M.
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