Estimating the difficulty level of a formal verification...

Details Estimating the difficulty level of a formal verification... Estimating the difficulty level of a formal verification...

2005-07-19

2008-11-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C714S738000

Reexamination Certificate

active

07458046

ABSTRACT:
Estimating the difficulty level of a verification problem includes receiving input comprising a design and properties that may be verified on the design. Verification processes are performed for each property on the design. A property verifiability metric value is established for each property in accordance with the verification processes, where a property verifiability metric value represents a difficulty level of verifying the property on the design. A design verifiability metric value is determined from the property verifiability metric values, where the design verifiability metric value represents a difficulty level of verifying the design.

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