Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-31
2003-09-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06618846
ABSTRACT:
BACKGROUND
Throughout the 1990's to the present, IC design and fabrication has progressed to smaller and smaller scales. Recent developments, for example, include the design of “systems on a chip,” or “SoCs,” using VDSM (“Very Deep Submicron”) technology. At VDSM dimensions, IC device sizes smaller than 0.25 microns (the sub-micron level, where one micron is one-millionth of a meter) are achieved. At such VDSM levels of integration, a number of design complexities arise. One of these is the well-known timing problems caused by capacitance effects generated within closely located conductive wires (hereafter, “interconnects”) interconnecting the semiconductor devices (hereafter, “devices”) constituting the integrated circuit. By way of background, a typical IC chip includes a semiconductor substrate containing upwards of a million devices of varying sizes (some devices of VDSM dimensions); the devices are in turn connected by interconnects running in metal layers layered atop the semiconductor substrate. A “metal layer structure” as used herein refers to the structure of metal layers
50
(
FIG. 1
) within which the interconnects are to be routed to connect the devices embedded in the semiconductor substrate. Interconnects are typically routed parallel to one another within each metal layer as illustrated in
FIG. 1
, although other configuration are sometimes used. In many common metal layer structures, the direction of the interconnects in adjacent layers is orthogonal. In addition, typical IC chips include a conductive substrate layer beneath the semiconductor substrate opposite to the metal layer structure that operates as a ground plane, as described next.
In
FIG. 1
, a typical metal layer structure
50
having five metal layers is illustrated. (It should be noted that different IC designs may employ differently configured metal layer structures—e.g., a three-metal layer structure where interconnects are routed in the same track direction for each metal layer, or a six-metal layer structure where a single layer includes interconnects routed orthogonally to the interconnects in the other five layers.) As shown in
FIG. 1
, five metal layers
50
—including layers M
1
, M
2
, M
3
, M
4
and M
5
respectively—are shown consecutively layered atop semiconductor substrate
54
(note that a ground plane beneath semiconductor substrate
54
is not shown). It should also be noted that the illustration in
FIG. 1
is an abstraction, and that many tracks in the lower metal layers, e.g., M
1
and M
2
, may actually be unavailable for routing due to blockages caused by macrocells (i.e., large logic devices such as a CPU) protruding from the semiconductor substrate
54
. Each metal layer M
1
through M
5
includes a set of parallel routing tracks that are illustrated as the dotted lines in M
1
-T through M
5
-T. M
1
-T through M
5
-T provide a top view of the parallel track structures (dotted lines) in metal layers M
1
through M
5
. (Some metal layer structures may have non-parallel routing tracks, and certain embodiments of the invention described below are not intended to be limited to any particular configuration of the routing tracks.) Thus, the routing tracks (M
1
-T for metal layer M
1
include routing track
56
running in a horizontal direction relative to the reader, when the reader views metal layer M
1
in the direction D (which is perpendicular to a plane of layer M
1
). Likewise, the routing tracks for M
2
-T include routing track
58
running in a vertical direction relative to the reader (i.e., orthogonal to the routing tracks in layers M
1
and M
3
). For purposes of this disclosure, metal layers will also be referred herein as “horizontal metal layers” or “vertical metal layers” depending on the routing track direction relative to the reader, unless otherwise noted.
Capacitance effects on a single interconnect
26
within a typical metal layer structure
18
may arise from a number of adjacent interconnects, as illustrated in FIG.
2
. In
FIG. 2
, metal layer structure
18
includes a ground plane
36
, first metal layer M
1
, second metal layer M
2
, third metal layer M
3
, and fourth metal layer M
4
. (Note that the semiconductor device layer is not shown but is normally placed between ground plane
36
and first metal layer M
1
). M
1
in turn includes interconnects
32
and
34
; M
2
includes interconnect
30
running orthogonal to interconnects
32
and
34
in M
1
; M
3
includes interconnects
24
,
26
and
28
running orthogonal to interconnect
30
; and M
4
includes interconnect
22
running orthogonal to interconnects
24
,
26
and
28
, and parallel to, for example, interconnect
30
in M
2
. It should be noted that such prior art metal layer structures
18
may be varied in terms of interconnect direction (e.g., interconnects may run diagonally or otherwise in a metal layer), number of metal layers (e.g., two to eight layers), the order of metal layers (e.g., adjacent layers may have the same interconnect direction), and the number and location of ground planes (the first or a second ground plane may be located between metal layers three and four).
As illustrated in
FIG. 2
, capacitance effects felt by interconnect
26
are shown by arrows, e.g., arrows
38
,
40
and
42
(other arrows are also shown but not labeled, and arrow
46
illustrates the capacitance effects generated between interconnect
24
and
28
). As shown, capacitance effects are generated within interconnect
26
by its neighboring interconnects
22
,
24
,
26
,
28
,
32
,
34
and
36
, and the ground plane
36
; the effects of capacitance flow in two directions (as illustrated by the arrows drawn as double-headed arrows), and thus interconnect
26
also causes capacitance effects on its neighboring interconnects
22
,
24
,
26
,
28
,
32
and
34
. The interconnects surrounding a given interconnect, e.g.
26
, whether a parallel interconnect in the same metal layer, e.g.,
28
and
24
in M
3
, or an orthogonal interconnect in a different metal layer, e.g.
22
and
30
in M
4
and M
3
respectively, will be referred to as neighboring interconnects for purposes of this disclosure. In general, the effects of capacitance may be estimated as a function of the distance (among other things) between neighboring interconnects, and therefore increased integration—causing the interconnects to be routed in closer proximity to one another—increases the capacitance effects between the neighboring interconnects. Depending on how signals are transmitted within the neighboring interconnects at a given moment in time, the capacitance effects on a given interconnect may either delay or accelerate the signal carried by it. In a worst case scenario, the arrangement of interconnects in a particular metal layer structure may cause signals to be delayed beyond acceptable timing thresholds, resulting in arbitrary and recurrent chip malfunction.
Two prior art techniques for estimating capacitance are currently prevalent. In one technique, the IC designer relies upon his or her accumulated experience to estimate the potential capacitance effects in each new layout. Applicant notes that this method lacks accuracy because, for example, two layouts are typically different both in architecture and in scale of integration (IC designs tend to progress to smaller scales of integration). In another technique, a layout is first completely routed, then analyzed for capacitance effects to retrieve relevant statistical data for optimizing the layout in a second routing iteration. Applicant notes that this method has the drawback of requiring the layout to be routed at least twice. In addition, Applicant notes that in typical applications, the prior art techniques use a single measure of capacitance to estimate capacitance for the entire design.
SUMMARY
In accordance with the present invention, a measure of congestion between interconnects of an integrated circuit (IC) chip being designed is estimated prior to routing of the interconnects through the chip. The estimated congestion for a portion of the chip is
Dimyan Magid
Silicon Valley Patent & Group LLP
Synopsys Inc.
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