Evaluating a validation vector for validating a network design

Details Evaluating a validation vector for validating a network design Evaluating a validation vector for validating a network design

2005-04-05

2005-04-05

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06877141

ABSTRACT:
Evaluating a validation vector includes receiving a network having nodes and a target set that includes one or more nodes of the network. The following steps are repeated until the nodes of the target set have been selected. A node is selected from the target set, and a tag is assigned to the node, where the tag represents an error of a value of a variable corresponding to the node. A test environment specifying a propagation path from an input, through the node, and to an output is generated. The test environment is translated into a validation vector, and the tag is propagated to the output according to the validation vector. After repeating the steps, coverage for the validation vectors is determined in accordance with the propagation to evaluate the one or more validation vectors.

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