Evaluation TEG for semiconductor device and method of...

Details Evaluation TEG for semiconductor device and method of... Evaluation TEG for semiconductor device and method of...

2006-02-14

2006-02-14

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07000201

ABSTRACT:
An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodes10and20having different electrode widths sufficiently large to disregard the length of the LOCOS birdbeak portion and an electrode30having an extremely small width substantially equal to the length of the birdbeak portion. All the electrode have the same length and are connected to test pads10a, 20a, and30a, respectively. The capacitance of a parasitic transistor is easily extracted by using the evaluation TEG and the evaluation of parameters causing the hump characteristics is become possible.

REFERENCES:
patent: 6470479 (2002-10-01), Yamamoto
patent: 6530066 (2003-03-01), Ito et al.
patent: 7-260867 (1995-10-01), None

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