Source synchronous timing extraction, cyclization and sampling
Split-gate DRAM with MuGFET, design structure, and method of...
Stage evaluation of a state machine
Stage mitigation of interconnect variability
Staged scenario generation
Stitched circuitry region boundary identification for...
Stress analysis method, wiring structure design method,...
Stress-managed revision of integrated circuit layouts
Structure for a duty cycle correction circuit
Structure for a stacked power clamp having a BigFET gate...
Structure for an absolute duty cycle measurement circuit
Structure for an integrated circuit design for reducing...
Structure for automated transistor tuning in an integrated...
Structure for couple noise characterization using a single...
Structure for dynamic latch state saving device and protocol
Structure for estimating power consumption of integrated...
Structure for fractional-N phased-lock-loop (PLL) system
Structure for glitchless clock multiplexer optimized for...
Structure for implementing speculative clock gating of...
Structure for initializing expansion adapters installed in a...