Structure for automated transistor tuning in an integrated...

Details Structure for automated transistor tuning in an integrated... Structure for automated transistor tuning in an integrated...

2011-08-30

2011-08-30

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S113000, C716S132000, C716S134000, C716S135000, C703S019000

Reexamination Certificate

active

08010932

ABSTRACT:
A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.

REFERENCES:
patent: 6209122 (2001-03-01), Jyu et al.
patent: 6735543 (2004-05-01), Douskey et al.
patent: 6766505 (2004-07-01), Rangan et al.
patent: 7278122 (2007-10-01), Willis
patent: 7302657 (2007-11-01), Lindkvist
Chung et al.; “Optimization of Power Dissipation and Skew Sensitivity in Clock Buffer Synthesis”; Proceedings of the 1995 International Symposium on Low Power Design Table of Content, Dana Point, CA; pp. 79-184; 1995.
Liu et al.; “Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing”; 2000 IEEE' pp. 209-214.

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