Staged scenario generation

Details Staged scenario generation Staged scenario generation

2011-07-05

2011-07-05

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Logic design processing

C716S106000

Reexamination Certificate

active

07975248

ABSTRACT:
A method of verifying integrated circuit designs, by constructing a series of atomic generators in a staged, hierarchical order, applying a lowest of the hierarchical generator stages to device level test cases of the verification process, applying a highest of the hierarchical generator stages to system level test cases of the verification process, reusing code written for and used in the lowest hierarchical generator stage in a next higher generator stage, creating a constraint scenario in the highest hierarchical generator stage, and injecting the constraint scenario into a next lower generator stage.

REFERENCES:
patent: 7725848 (2010-05-01), Nebel et al.
patent: 7779374 (2010-08-01), Hamid et al.

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