Stress analysis method, wiring structure design method,...

Details Stress analysis method, wiring structure design method,... Stress analysis method, wiring structure design method,...

2011-04-05

2011-04-05

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Testing or evaluating

Reexamination Certificate

active

07921401

ABSTRACT:
A stress analysis method is provided: including dividing, by using a division unit, an inside of a chip into a plurality of analysis areas, deriving, by using a composite property derivation unit, a composite property into which physical property values of a plurality of materials included in an analysis area are compounded, about each of the plurality of analysis areas on the basis of wiring structure data for each of the plurality of analysis areas, and creating, by using a stress analysis unit, a three-dimensional model of a finite element method which uses each analysis area as an element, to apply the composite property to each element, and to perform a stress analysis.

REFERENCES:
patent: 5579249 (1996-11-01), Edwards
patent: 5610833 (1997-03-01), Chang et al.
patent: 5768156 (1998-06-01), Tautges et al.
patent: 6282692 (2001-08-01), Rubin
patent: 6304794 (2001-10-01), Nishimine et al.
patent: 6594800 (2003-07-01), Chang et al.
patent: 6813749 (2004-11-01), Rassaian
patent: 6958542 (2005-10-01), Hasunuma et al.
patent: 7194711 (2007-03-01), Chandra
patent: 7505884 (2009-03-01), Dadkhah et al.
patent: 7558639 (2009-07-01), Rassaian et al.
patent: 7587691 (2009-09-01), Sutjahjo et al.
patent: 2003/0055612 (2003-03-01), Amakai et al.
patent: 2003/0154451 (2003-08-01), Rassaian
patent: 2004/0044511 (2004-03-01), Sekido et al.
patent: 2005/0066301 (2005-03-01), Lorenz et al.
patent: 2005/0167842 (2005-08-01), Nakamura et al.
patent: 2006/0036984 (2006-02-01), Mukaihira
patent: 2007/0007618 (2007-01-01), Hasunuma et al.
patent: 2008/0168413 (2008-07-01), Kakino et al.
patent: 2010/0023899 (2010-01-01), Moroz et al.
patent: 2003-167929 (2003-06-01), None
Zampino, Marc A., “Vibration Analysis of an Electronic Enclosure using Finite Element Analysis”, 1995. IEEE, pp. 328-333.

Affiliated with

Also associated with

Rating

Stress analysis method, wiring structure design method,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stress analysis method, wiring structure design method,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stress analysis method, wiring structure design method,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2699763