Source synchronous timing extraction, cyclization and sampling

Details Source synchronous timing extraction, cyclization and sampling Source synchronous timing extraction, cyclization and sampling

2011-08-30

2011-08-30

Memula, Suresh (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Testing or evaluating

C716S113000, C703S014000, C703S015000, C703S016000, C703S017000, C703S019000, C714S738000, C714S741000

Reexamination Certificate

active

08010933

ABSTRACT:
A method for injecting timing irregularities into test patterns self-generated by a device under test (DUT) includes obtaining timing irregularities, receiving the test patterns generated by the device under test driven from output drivers of the DUT, injecting the timing irregularities into the test patterns to generate test patterns with timing irregularities injected therein, and applying the test patterns with timing irregularities injected therein to input receivers of the DUT. A tester is configured to test loopback functionality of a device under test (DUT) utilizing a timing irregularities injection apparatus which receives timing irregularity data readable by the tester and test data generated by the DUT, and injects the timing irregularity data into the test data for application to the DUT.

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