Stitched circuitry region boundary identification for...

Details Stitched circuitry region boundary identification for... Stitched circuitry region boundary identification for...

2011-06-07

2011-06-07

Lin, Sun J (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S050000, C716S124000, C716S139000

Reexamination Certificate

active

07958482

ABSTRACT:
Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.

REFERENCES:
patent: 5301124 (1994-04-01), Chan et al.
patent: 5837557 (1998-11-01), Fulford, Jr. et al.
patent: 6048785 (2000-04-01), Fulford, Jr. et al.
patent: 6150840 (2000-11-01), Patel et al.
patent: 6194105 (2001-02-01), Shacham et al.
patent: 6225013 (2001-05-01), Cohen et al.
patent: 6335635 (2002-01-01), Patel et al.
patent: 6690076 (2004-02-01), Fossum et al.
patent: 6782499 (2004-08-01), Osada et al.
patent: 7093143 (2006-08-01), Ito et al.
patent: 7117466 (2006-10-01), Kalafala et al.
patent: 7141883 (2006-11-01), Wei et al.
patent: 7161828 (2007-01-01), Cummings et al.
patent: 2001/0026172 (2001-10-01), Leenstra et al.
patent: 2005/0246116 (2005-11-01), Foreman et al.
patent: 2006/0071691 (2006-04-01), Garlepp
patent: 2009/0276739 (2009-11-01), Leidy et al.
patent: 11176937 (1999-02-01), None
patent: 2005141434 (2005-06-01), None
Dunham et al., “Stitched IC Chip Layout Methods, Systems and Program Product,” U.S. Appl. No. 11/678,069, Feb. 23, 2007, pp. 1-33.
Dunham et al., “Stitched IC Chip Layout Methods, Systems and Program Product,” PCT/US08/54705, Feb. 22, 2008, 29 pages.
Davis, D.E., “Stitching Technique for Electron Beam Lithography System,” IBM Technical Disclosure Bulletin, Oct. 1978, pp. 1875-1876.
Davis, D.E., “Field Stitching Method,” IBM Technical Disclosure Bulletin, Jun. 1979, pp. 114-115.
Chen et al., “Static Timing: Back to Our Roots”, IBM Research, 7 pages.
Moore, R.D., “Efficient Stitching Method,” IBM Technical Disclosure Bulletin, Jan. 1978, vol. 20, No. 8, pp. 3104-3105.
U.S. Appl. No. 11/849,461, Office Action, Aug. 4, 2009, 11 pages.
U.S. Appl. No. 11/678,069, filed Feb. 23, 2007, Response to 312 Amendment filed Dec. 10, 2009, dated Dec. 18, 2009.
U.S. Appl. No. 11/678,069, filed Feb. 23, 2007, 312 Amendment filed Dec. 10, 2009.
U.S. Appl. No. 11/849,461, filed Sep. 4, 2007, Notice of Allowance dated Dec. 8, 2009.
U.S. Appl. No. 11/678,069, filed Feb. 23, 2007, Notice of Allowance dated Dec. 2, 2009.
U.S. Appl. No. 11/678,069, Amendment to Office Action dated Aug. 4, 2009, filed Nov. 4, 2009.
U.S. Appl. No. 11/849,461, filed Sep. 4, 2007, Amendment to Office Action dated Aug. 4, 2009, filed Nov. 4, 2009.
Lin, U.S. Appl. No. 12/112,336, Office Action Communication, BUR920080086US2, Jan. 11, 2011, 13 pages.
Lin, U.S. Appl. No. 12/112,336, Notice of Allowance and Fees Due, Apr. 20, 2011, 9 pages.

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