Stage evaluation of a state machine

Details Stage evaluation of a state machine Stage evaluation of a state machine

2011-05-17

2011-05-17

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Testing or evaluating

Reexamination Certificate

active

07945886

ABSTRACT:
The present invention provides a method a system for facilitating enhanced processing of state diagrams in a state diagram environment. The method may include top-down processing a current state in a state diagram environment; determining whether processing of the current state results in an exception event; and passing the exception event to a superstate that includes the current state when it is determined that the current state results in an exception event. The superstate may be made the current state and it may be determined whether the current state can handle the exception event. When it is determined that the current state cannot handle the exception event, it may be determined whether the current state has a second superstate that includes the current state. An error event may be output from the state diagram environment when it is determined that the current state does not have a second superstate.

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The MathWorks, “Stateflow and Stateflow® Coder, For Use with Simulink®, User's Guide, Version 6,” The MathWorks, Inc. (2004).
International Preliminary Report on Patentability for Application No. PCT/US2006/037985, dated Dec. 17, 2007.

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