Structure for a stacked power clamp having a BigFET gate...

Details Structure for a stacked power clamp having a BigFET gate... Structure for a stacked power clamp having a BigFET gate...

2011-08-30

2011-08-30

Rossoshek, Helen (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S100000, C716S103000, C716S104000, C716S106000, C716S109000, C716S110000, C716S111000, C716S123000, C257S173000, C257S355000, C257S360000, C257S503000, C257S363000

Reexamination Certificate

active

08010927

ABSTRACT:
Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

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Response to first Office Action dated Feb. 24, 2010, regarding related U.S. Appl. No. 11/865,820, filed Oct. 2, 2007, entitled “Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit,” Robert J. Gauthier and Junjun Li.
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U.S. Appl. No. 11/865,820, filed Oct. 2, 2007, entitled Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit, Inventors: Robert J. Gauthier and JunJun Li.
First Office Action dated Nov. 25, 2009, regarding related U.S. Appl. No. 11/865,820, filed Oct. 2, 2007, entitled Stacked Power Clamp Having a BigFET Gate Pull-Up Circuit, Robert J. Gauthier and Junjun Li.

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