Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2008-04-30
2011-12-13
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
C716S101000, C713S500000, C713S600000
Reexamination Certificate
active
08078999
ABSTRACT:
A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register. The design structure includes a netlist describing the apparatus for implementing speculative clock gating of digital logic circuits included in a multiple stage pipeline design.
REFERENCES:
patent: 6009533 (1999-12-01), Zick
patent: 6247134 (2001-06-01), Sproch et al.
patent: 6393579 (2002-05-01), Piazza
patent: 6609209 (2003-08-01), Tiwari et al.
patent: 6745336 (2004-06-01), Martonosi et al.
patent: 6906554 (2005-06-01), Chen
patent: 7359846 (2008-04-01), Fernandez
patent: 2003/0149905 (2003-08-01), Santhanam et al.
patent: 2004/0143727 (2004-07-01), McDonald
patent: 2006/0136854 (2006-06-01), Arp et al.
patent: 2008/0282212 (2008-11-01), Dennison et al.
patent: 2009/0106616 (2009-04-01), Ozer et al.
U.S. Appl. No. 12/019,718; Notice of Allowance; Date Filed: Jan. 25, 2008; Date Mailed: Feb. 15, 2011.
U.S. Appl. No. 12/019,718; Non-Final Office Action; Date Filed: Jan. 25, 2008; Date Mailed: Oct. 25, 2010.
Blaner Bartholomew
Brown Mary D.
Burky William E.
Venton Todd A.
Cantor & Colburn LLP
Chiang Jack
Dimyan Magid
International Business Machines - Corporation
LeStrange Michael
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