EEPROM cell array with tight erase distribution
EEPROM cell array with tight erase distribution
EEPROM cell having improved topology and reduced leakage current
EEPROM cell having reduced capacitance across the layer of tunne
EEPROM cell having reduced cell area
EEPROM cell on SOI
EEPROM cell structure and architecture with increased capacitanc
EEPROM cell structure and array architecture
EEPROM cell testing circuit
EEPROM cell using conventional process steps
Eeprom cell with asymmetric thin window
EEPROM cell with channel hot electron programming and method for
EEPROM cell with field-edgeless tunnel window using shallow tren
EEPROM cell with improved tunneling properties
EEPROM cell with self-aligned tunneling window
EEPROM cell with the drain diffusion region self-aligned to the
EEPROM cell with trench coupling capacitor
EEPROM cell with tunneling across entire separated channels
EEPROM cell with tunneling at separate edge and channel regions
EEPROM device and method for fabricating same