Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-10-19
2004-02-10
Jackson, Jerome (Department: 3874)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S318000, C257S321000, C257S322000, C257S347000
Reexamination Certificate
active
06690056
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of floating gate devices on Silicon On Insulator (SOI).
BACKGROUND OF THE INVENTION
General
Electronic devices perform several functions, including digital, analog and memory. Memory devices fall into two broad categories: volatile and non-volatile, with the distinction that volatile memory loses its information when power is removed while non-volatile memory does not.
Multiple types of non-volatile (NV) memory have been used over the years, with the most common based on magnetic devices such as magnetic core, tape or discs or optical devices such as CD-ROM. Such devices offer high density and low cost, but cannot be integrated onto integrated circuits. They are therefore typically used in computer systems as separate modules, but cannot provide non-volatile memory as an integral part of an integrated circuit, or chip.
Including non-volatile storage of information on board a chip has become increasingly important. With such capability, standard chips can be permanently programmed to perform specialized functions; variable coefficients can be permanently stored; and critical data can be backed up during operation to improve system reliability. Additionally, on-chip NV memory enables a single chip to be manufactured in large volume for multiple markets, with customization provided by programming, either at the manufacturer or by the customer. This provides cost efficiency from the large volume production to lower volume, customized applications. NV memory is particularly important for battery operated systems such as cellular phones and portable consumer electronics where both customization and information storage is required and must survive complete loss of power.
Uses of on-chip NV memory continue to expand with its availability. Many wireless systems require significant permanent customization to set radio performance specifications (e.g., frequency plans, gain levels, internal operating conditions, A/D performance, account information, security codes and software changes or upgrades). New markets include so-called IC cards used as credit cards, pre-paid purchase cards, medical records storage and RF ID tags. Other new applications include content addressable memory, security verification, package tracking, commercial satellites and many more. The key to these new applications is to be able to include NV memory with as many other microelectronic functions as possible.
Storage Cells
The original NV memory was commonly called Floating-gate Avalanche-injection MOS (FAMOS) and is described in U.S. Pat. Nos. 3,500,142 and 3,919,711. In this device, a polysilicon gate transistor was made without electrical contact to the gate conductor. By applying a high voltage to the drain of an N-channel transistor, small currents were amplified through avalanche gain, creating high energy (or “hot”) electrons or holes. The combination of high energy and large voltage on the drain forced some of the carriers to penetrate through the gate oxide and onto the electrically floating polysilicon gate conductor. Once charged, the gate maintained the transistor in a conducting, or “on”, state which represented a stored bit of information. Initial products were based on bulk Si PMOS transistors storing electrons on the gate. However, no integrated electrical mechanism was available to inject electrons or to remove holes thereby providing an erase function.
While effective at writing, the lack of an electronic mechanism to erase or remove the stored charge was a severe limitation. Hence, this class of device became known as an Electrically Programmable Read Only Memory, or EPROM. The erasing mechanism devised was to apply ultraviolet light which gave the stored charge sufficient energy to return to the silicon and be dissipated, hence the name UVEPROM. UV erasing was time consuming, required special equipment and device packaging and perhaps worst of all, it required removal of the device from the system for reprogramming. The value of NV memory was so great that these drawbacks did not prevent UVEPROM from becoming a very successful product. However, the drawbacks led to a search for a next generation of device, the Electrically Erasable PROM, called EEPROM or E
2
PROM and often referred to simply as E-squared. By providing electrically erasable memory, the UV light, special packaging and removal requirements were eliminated and NV memory became an industry segment unto itself, spawning numerous companies.
In EEPROM, a second polysilicon layer is placed above or near the floating storage node and separated by a very thin, high quality silicon dioxide layer, as described in many U.S. Patents, including U.S. Pat. Nos. 3,996,657, 5,587,947 and 5,689,459. Writing occurs by applying a drain source voltage of sufficient magnitude to create source-drain current with channel hot electrons (CHE) of sufficient energy and momentum to penetrate the gate oxide. Erasing occurs by applying a high voltage to the second gate, sufficiently high electric fields can be generated to induce the quantum mechanical tunneling phenomenon (Fowler-Nordheim), in which a charged particle penetrates a thin insulating layer. With the second gate, an electrical erasing mechanism is integrated onto the chip, thereby eliminating the need for UV light and more importantly, allowing in-system re-programming. However, process complexity increases and on-chip high voltages have to be generated, controlled and routed. The high electric field eventually causes damage to the thin oxide layer, creating reliability issues. Also, the erasing mechanism is an inherently unstable process which can cause over-erasing (and subsequent under-writing) and other problems. Sophisticated control circuits are required to ensure proper operation.
Multiple variations on the EEPROM writing and erasing mechanisms have been defined and used. Processing and layout details affect performance, speed and reliability. Control of the thin oxide layers must be to the highest standards, often limiting yield and manufacturability. Many large chips, such as high performance microprocessors and digital signal processors would benefit from inclusion of EEPROM, but the process and design complexity can make this prohibitively expensive. However, in specialized processing facilities, large NV memory chips known as Flash memory use a variation of EEPROM storage cells and are manufactured cost effectively.
A recent variation on the standard EEPROM cell is the so-called stepped channel device, as described in U.S. Pat. No. 5,780,341. In this cell, a shallow step is introduced into the channel region of the writing transistor, making the drain slightly lower than the source. As electrons transit from source to drain, they encounter the step. The step enhances CHE injection mechanism thereby completing the writing mechanism at lower voltage. The detailed mechanisms are described in the references, but can be thought of as a microscopic solid state electron implanter. By adjusting the size and location of the step along with the transistor design, electrons can be written effectively. However, this still leaves the requirement to erase the cell, which is done by conventional Fowler-Nordheim tunneling as found in conventional EEPROM.
Processes
EEPROM storage cells are inherently MOS devices and can be integrated into any MOS process. However, the high voltages necessary for programming add additional requirements to the process to deal with routing of the high voltage signals. In standard CMOS, regions between transistors are called the field and constitute a parasitic MOS transistor. If this region is improperly designed so-called field inversion can occur, thereby improperly shorting together two or more adjacent transistors. High voltage on interconnects increases this problem and forces changes to the CMOS process. Additionally, CMOS circuits can exhibit a phenomenon known as latch-up in which a large, stable current can be triggered which can either destroy the chip or at least force power down. Modern CMOS processes nor
Cable James S.
Reedy Ronald E.
Fenty Jesse A.
Fuierer Marianne
Hultquist Steven J.
Jackson Jerome
Peregrine Semiconductor Corporation
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