EEPROM cell having improved topology and reduced leakage current

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257314, 257315, H01L 2976, H01L 29788

Patent

active

057367655

ABSTRACT:
An EEPROM cell of reduced leakage current during erasure and improved cell topology includes a first conductivity type substrate having a channel region, a trench formed in the channel region of the substrate, first spacers formed on opposed sidewalls of the trench, and a gate oxide film formed at the bottom of the trench between the first spacers. Second conductivity type source/drain regions are formed in the substrate at opposite side of the trench. A tunneling oxide film is further provided on the substrate overlying the drain region and proximate the trench. An insulation film is provided over the entire substrate surface except the trench and the tunneling oxide film. In addition, a floating gate is formed on the insulation film over the source and drain regions, as well as the gate oxide film at the trench bottom. Second spacers are provided on the insulation film at opposed side surfaces of the floating gate. A dielectric film is then provided on the surface of the floating gate and the second spacers, and a control gate is formed on the dielectric film.

REFERENCES:
patent: 4990979 (1991-02-01), Otto
patent: 5173436 (1992-12-01), Gill et al.
patent: 5315142 (1994-05-01), Acovic et al.
patent: 5359218 (1994-10-01), Taneda
patent: 5486714 (1996-01-01), Hong
patent: 5506431 (1996-04-01), Thomas
patent: 5583360 (1996-12-01), Roth et al.

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