Eeprom cell with asymmetric thin window

Details Eeprom cell with asymmetric thin window Eeprom cell with asymmetric thin window

2001-05-01

2002-04-09

Booth, Richard (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S264000, C438S286000

Reexamination Certificate

active

06369422

ABSTRACT:

TECHNICAL FIELD
The invention relates to floating gate, nonvolatile, electrically alterable memory cells, and in particular to a miniaturized memory cell and method of making same.
BACKGROUND OF THE INVENTION
Nonvolatile memory cells typically use an oxide window to transfer charge to and from a floating gate. The logic state of the memory cell is determined by the presence or absence of charge of the floating gate. The transfer rate of charge to and from the floating gate is dependent on applied voltage potentials, on the relative size of the oxide window, the oxide window thickness, etc.
Nonvolatile memory cells require not just a reference high potential, Vcc supply voltage for operation, but also require at least one high program and erase voltage, Vpp, which is for example approximately 15-16 volts and typically two or three times the magnitude of Vcc. As integrated circuit devices such as cells comprising memory transistors and select transistors are scaled down, not only are the dimensions of their continuant elements reduced, but their applied voltages must also be reduced to maintain proper device operation and to not damage the scaled down device. In nonvolatile memory cells, the program and erase voltage Vpp cannot be reduced too much since it must remain above Vcc by some predetermined large margin. By designing a cell such that it requires a relatively high Vpp voltage in order to induce programming and erase operations, the chances of the cell being inadvertently programmed or erased by the standard Vcc voltage rail is reduced. This is especially true when small devices, which use a relatively low reference voltage Vcc
1
, are interfaced with large devices that used a relatively higher reference voltage Vcc
2
. If the higher reference voltage Vcc
2
of the large devices is of comparable potential as the program and erase Vpp voltage of the smaller devices, then a memory cell of the smaller devices may have its data inadvertently altered. The program and erase Vpp voltage of the smaller devices must therefore remain a safe margin higher than Vcc
1
or Vcc
2
.
As the dimensions of a cell are reduced, the effects of the reference voltages Vcc and Vpp are amplified. If the magnitude of Vcc and Vpp are not reduced, then the scaled down cell behaves as if a higher voltage were being applied resulting in a degradation in the cell's performance and reliability. In the case of nonvolatile memories, since the Vpp value of a scaled down memory cell remains relatively high, the affect of the charge transfer oxide window is magnified as the dimensions of the memory cell are reduced. For example, the amount of charge transfer per unit area of the oxide window may remain constant or even increase as the floating gate, control gate, and drain are reduced. This causes a non-uniform scaling of the memory cell resulting in a limited amount of permissible scaling. In order to compensate for the relatively stronger influence of Vpp, the dimensions of the oxide window should ideally be reduced further than the other elements of the cell. The minimum oxide window, however, is typically limited by the minimum feature size resolution of the manufacturing equipment being used to construct the memory cell. This places a finite limit on the minimum size achievable for the oxide window beyond which it may not be reduced.
Further complicating the construction of a scaled memory cell is the complicated structure of the cell itself. It is often desirable that the location of the oxide window be between a select transistor and a memory transistor. This requires many masking steps to form the cell, which compounds to the problem of the finite size of the oxide window when attempting to construct a scaled down nonvolatile memory cell.
With reference to
FIG. 1
, a nonvolatile memory transistor, which is an integral part of a memory cell, resembles a typical MOS transistor in that it includes a source region
11
and drain region
12
in a substrate
15
. The area between the source
11
and drain
12
define the length dimension of the memory transistor's channel region. Characteristic of a stack gate, nonvolatile memory transistor is a control gate
21
over a floating gate
19
on gate oxide
23
overlying channel region
17
and partly covering the source
11
and drain
12
regions. Floating gate
19
is separated from a control gate
21
by an inter-poly oxide
25
. More characteristic of electrically alterable nonvolatile memory cells in general is an oxide window
27
through which charge is transferred to and from floating gate
19
. In essence, the dimensions of oxide window
27
define the size of the cell's charge transfer region. As will be explained below, this characteristic is an obstacle to the construction of a memory cell of minimum feature size.
With reference to
FIG. 2
, a cross-sectional view along lines
2
—
2
of
FIG. 1
shows that the transistor is constructed between two opposing field oxide regions
29
. The separation between field oxide regions
29
defines the width direction of the memory transistor. Floating gate
19
is shown to span the width of the channel region and to partly cover field oxide region
29
. Similarly, control gate
21
is implemented as a polysilicon strip extending perpendicular to the length of the memory transistor. Oxide window
27
, which in this case overlays drain region
12
, extends from one field oxide region
29
to the other.
This cell architecture, which is more fully recited in U.S. Pat. No. 5,086,325 assigned to the assignee of the present invention, simplifies construction of the memory transistor of a cell by having the width of the oxide window defined by the minimum spacing between field oxide regions
29
. This architecture has traditionally resulted in a cell of compact size, but as cells sizes are further reduced, it becomes necessary to bring field oxide regions
29
even closer together to maintain proper scaling performance. It has been found, however, that as field oxide regions
29
are brought very close together, oxide buckling that can distort the window oxide may occur. This can lead to premature failure of a cell, and thus poses a limitation to the amount of scaling permissible with this architecture.
With reference to
FIG. 3
, U.S. Pat. No. 5,904,524 addresses this problem by removing its oxide window
31
out from between the field oxide regions
33
and
35
that define the width of the cell channel. The cell is defined by three active areas
41
,
43
, and
45
. The source, drain, and channel regions of the memory cell are within active area
43
, the control gate
47
is coupled to floating gate
49
in active area
41
, and floating gate
49
overlies the channel region in active area
43
, and overlies the oxide window
31
in active area
45
. Since the channel area is in active area
43
and the oxide window
31
is not in active area
43
, field oxide regions
33
and
35
may be brought closer together to form a small width channel without causing buckling of oxide window
31
. The '524 patent explains that this permits easier scaling of the memory cell since oxide window
31
is no longer affected by the narrowing of the cell channel width. This cell architecture, however, requires three adjacent active areas
41
,
43
, and
45
isolated by interposed field oxide regions
33
and
35
, and is therefore not a very compact architecture.
With reference to
FIG. 4
, a different cell architecture discussed in U.S. Pat. No. 5,066,992 and assigned to the assignee of the present invention shows a memory cell with one side of its oxide window
51
aligned to floating gate
53
and control gate
55
. The width of oxide window
51
still extends across the width of the channel such that miniaturization of the cell is still limited by the how close the surrounding field oxide regions, not shown, may be brought together. However, the length of oxide window
51
is adjusted by the placement of floating gate
53
and control gate
55
. This is because floating gate
53
is formed by the use of

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