EEPROM cell structure and array architecture

Details EEPROM cell structure and array architecture EEPROM cell structure and array architecture

2005-06-14

2005-06-14

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S316000, C257S320000, C438S201000, C438S211000, C438S257000

Reexamination Certificate

active

06906376

ABSTRACT:
An EEPROM cell device on a substrate is achieved. The device comprises, first, a selection transistor having gate, drain, source, and channel. The drain is defined as a cell bit line. An isolation transistor has gate, drain, source, and channel. The source is defined as a cell source line. Finally, a floating gate transistor has control gate, floating gate, drain, source, and channel. The drains and sources of each transistor comprise a diffusion layer in the substrate. The channels of each transistor comprise the substrate. The floating gate transistor drain is coupled to the selection transistor source. The floating gate transistor source is coupled to the isolation transistor drain. The device is programmed and erased by charge tunneling between the floating gate and the floating gate transistor channel. The device may further comprise an isolation well underlying the diffusion layer. A two transistor EEPROM cell is disclosed. Several array architectures using the EEPROM cell are disclosed.

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