EEPROM cell with tunneling at separate edge and channel regions

Details EEPROM cell with tunneling at separate edge and channel regions EEPROM cell with tunneling at separate edge and channel regions

1998-12-22

2001-09-25

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S318000, C257S326000, C365S185010, C365S185050, C365S185260, C365S185280

Reexamination Certificate

active

06294810

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor devices, and more particularly, to an electrically erasable programmable read only memory (“EEPROM”) cell.
2. Description of Related Art
The semiconductor community faces increasingly difficult challenges as it moves into production of semiconductor devices at feature sizes approaching 0.1 micron. Cell designs for typical semiconductor devices must be made more reliable, scalable, cost effective to manufacture and able to operate at lower power in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one of such semiconductor devices that must meet these challenges.
EEPROM devices are generally known as read-only memory in which the memory cells that store information may be erased and reprogrammed electrically. An EEPROM cell is typically made up of three separate transistors, namely, a write transistor, a sense transistor and a read transistor. The EEPROM cell is able to be programmed, erased and read by removing or adding electrons to a floating gate. Thus, in one example, the floating gate is programmed by removing free electrons from the floating gate and thereby giving the floating gate a positive charge. When it is desired to erase the EEPROM cell in this example, the floating gate is given a net negative charge by injecting electrons onto the floating gate. The read operation is performed by reading the state (current) of the sense transistor. In order to give the floating gate a positive charge (program) or negative charge (erase), electron tunneling, for example using the well-known Fowler-Nordheim tunneling technique, may be performed by applying the appropriate voltage potentials between the floating gate and a region, such as a drain region, of a transistor. Upon applying the appropriate voltage potentials, electron tunneling occurs through a tunnel oxide layer between the floating gate and the region.
As the feature sizes of EEPROM cells are scaled downward, the prior art EEPROM cells exhibit certain scaleablity, cost and reliability limitations. First, the manufacturing process for a smaller EEPROM cell becomes more complex and, accordingly, manufacturing costs rise as transistor channel lengths are reduced. For example, as the channel length of a transistor of the EEPROM cell is scaled downward, the thickness of the gate oxide overlying the channel must also be reduced since the gate oxide thickness must be scaled with the channel length. In view of the fact that EEPROM cells already have a complex process to form multiple oxide thicknesses, additional oxide thicknesses for the transistors would add additional steps to further complicate the manufacturing process and thereby increase manufacturing costs.
In addition to this scaling problem, reliability problems also exist with previous EEPROM cells. First, the EEPROM cell is typically both programmed and erased through one tunnel oxide window of a transistor region that may deteriorate the cell quickly. In general, the tunnel oxide window deteriorates after tens of thousands of program/erase cycles and that deterioration cycle is shortened by only using the tunnel oxide window for both programming and erasing operations. Thus, the use of the window for both programming and erasing of the EEPROM cell causes the cell to be significantly less reliable. A further reliability limitation of previous EEPROM cells is that the tunnel oxide window is less reliable because it is formed over a highly doped program junction (PRJ). The high doping concentration of the PRJ degrades the surface immediately above the PRJ and thereby reduces the EEPROM cell's reliability. A still further limitation of the EEPROM cell is that the voltages needed to program, erase and read the cell are high due to the relatively large feature sizes of the cell. Thus, in order to achieve lower voltages to operate the EEPROM cell, feature sizes of the cell must be scaled downward.
Thus, a need exists for a redesigned EEPROM cell that (1) does not add costly steps to the manufacturing process, (2) does not suffer from reliability problems caused by both programing and erasing through one tunnel oxide window, (3) does not deteriorate through use of a PRJ oxide, and (4) operates at a lower power by using smaller feature sizes.
SUMMARY OF THE INVENTION
An EEPROM cell is described that is programmed and erased by electron tunneling at separate transistor regions, namely at an edge of a tunneling transistor drain and a sense transistor channel. The EEPROM cell has three transistors formed in a semiconductor substrate: a tunneling transistor, a sense transistor and a read transistor. The tunneling transistor has a tunneling source, a tunneling drain, and a tunneling channel between the tunneling source and the tunneling drain. The tunneling source and the tunneling drain have a second conductivity type that is opposite a first conductivity type of the semiconductor substrate. A tunnel oxide layer is formed over the tunneling channel, the tunneling source and the tunneling drain. Between the tunneling transistor and the sense transistor is a program junction region, also formed in the semiconductor substrate, and separated from the tunneling transistor by a first oxide and separated from the sense transistor by a second oxide. The program junction region, having the second conductivity type, also has a program junction oxide layer overlying the program junction region. The sense transistor is also formed in the semiconductor substrate. The sense transistor has a sense source, a sense drain and a sense channel between the sense source and the sense drain where both the sense source and the sense drain have the second conductivity type. A sense tunnel oxide layer overlies the sense channel, the sense source and the sense drain. The read transistor, also formed in the semiconductor substrate, is electrically coupled to the sense transistor through the sense drain. A floating gate overlies the tunnel oxide layer, the program junction oxide layer and the sense tunnel oxide layer. Electron tunneling occurs through the tunnel oxide layer overlying an edge of the tunneling drain upon incurrence of a sufficient voltage potential between the floating gate and the tunneling drain. Electron tunneling also occurs through the sense tunnel oxide layer overlying the sense channel upon incurrence of a sufficient voltage potential between the floating gate and the sense channel.
The EEPROM cell of the present invention provides electron tunneling through the sense tunnel oxide layer overlying the sense channel to occur across the entire portion of the sense channel. The EEPROM cell of the present invention further allows erasing only at the edge of the tunneling drain and programming only across the sense channel to thereby separate the program and erase operations and thereby increase the EEPROM cell reliability. The EEPROM cell further has reduced thicknesses for the tunnel oxide layer, the program junction oxide layer, the sense tunnel oxide layer and the read gate oxide layer to improve scaleablity and reduce operating voltages of the EEPROM cell of the present invention.


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