EEPROM cell structure and architecture with increased capacitanc

Details EEPROM cell structure and architecture with increased capacitanc EEPROM cell structure and architecture with increased capacitanc

1991-10-17

1994-07-26

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257317, 257408, H01L 2968

Patent

active

053329147

ABSTRACT:
An EEPROM memory cell structure and architecture that achieve very high speed programming with low power. The cell has four control terminals. The structure utilizes programming and erasure by electron tunneling only. The structure allows programming by hot electrons from the substrate and erasure by electron tunneling between polysilicon layers. A process for forming the structure results in final feature size for the floating gate and the space between floating gates in a memory array to be significantly smaller than achievable by photolithography equipment's resolution capability.

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R. Kazerounian et al., "A 5 Volt High Density Poly-Poly Erase Flash EEPROM Cell", IEDM-Dec. 11 1988 pp. 436-439.
Yoshikawa et al. "An Asymmetrical Lightly-Doped Source (ALDS) for Virtual Ground High Density EPROMs", IEDM-Dec. 11, 1988 pp. 432-435.
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T. Mizuno et al. Si.sub.3 N.sub.4 /SiO.sub.2 Spacer Induced High Reliability in LDDMOSFET and Its Simple Degradation Model, IEDM-88 (See FIG. 1).

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