Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-04-18
2003-06-03
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000
Reexamination Certificate
active
06573557
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure of an EEPROM cell made of one-layer polycrystalline silicon.
2. Description of the Related Art
Conventionally, for the purpose of forming an EEPROM cell on a silicon semiconductor substrate by using one-layer polycrystalline silicon, the following structure has been used.
As shown in
FIG. 6
, there is a select gate transistor constituted by a first impurity diffusion layer
22
and a second impurity diffusion layer
23
separated by a first channel region
21
, and a select gate electrode
24
formed over the first channel region
21
through an insulating film and made of, for example, polycrystalline silicon.
There is a cell transistor constituted by the second impurity diffusion layer
23
and a third impurity diffusion layer
26
separated by a second channel region
25
, and a floating gate electrode
27
formed over the second channel region
25
and the second impurity diffusion layer through an insulating film and made of, for example, polycrystalline silicon. Here, in the insulating film region on the second impurity diffusion layer
23
, a first tunnel insulating film region
28
made of a thin insulating film is formed under the floating gate electrode
27
.
The select gate transistor and the cell transistor are arranged so that the first channel region
21
and the second channel region
25
are formed to be parallel and on a line, and a cell source line becomes a diffusion wiring of the third impurity diffusion layer
26
.
Next, an impurity diffusion layer, which becomes a control gate, is formed in parallel with the channel direction of the first channel region
21
and the second channel region
25
. At this time, since the select gate electrode intersects with the control gate diffusion layer, the control gate comes to have a fourth impurity diffusion layer
30
and a fifth impurity diffusion layer
31
separated by a third channel region
29
parasitically formed.
Moreover, the floating gate electrode,
27
is formed, which is connected with the gate of the cell transistor through a second tunnel insulating film region
32
made of a thin insulating film in an insulating film region on the fifth impurity diffusion layer
31
.
Finally, a bit line wiring is connected with the first impurity diffusion layer
22
through a bit line contact
33
, and a control gate wiring is connected with the fourth impurity diffusion layer
30
through a control gate contact
34
.
In the conventional structure, since the impurity diffusion layer region of the cell transistor and the select gate transistor, and the impurity diffusion layer region of the control gate wiring are arranged in parallel with each other, there have been problems as set forth below.
1. Since the select gate electrode passes over the control gate wiring, a parasitic transistor is formed in front of the control gate, so that a writing voltage given to the control gate is lowered.
2. Since the parasitic transistor exists, and separation is made to the cell source wiring made of the impurity diffusion layer, it is difficult to reduce a memory cell area, and in order to reduce the area, for example, the wiring is made to have three layers or four layers, so that the number of steps is increased.
3. Since the cell source wiring is made of the impurity diffusion layer, when a cell is made minute, a source resistance is increased, so that it is difficult to effectively obtain a cell current.
SUMMARY OF THE INVENTION
An object of the invention is to eliminate the foregoing problems by improving the conventional structure.
According to the invention, a semiconductor device has such a structure that a cell transistor and a select gate transistor are arranged perpendicularly to each other, a select gate electrode and a control gate wiring are arranged in parallel with each other, and a cell source wiring is made of a metal wiring through a contact. Thus, this structure has functions as set forth below.
1. Since a parasitic transistor is not formed on the control gate wiring, a writing voltage can be effectively given to a control gate.
2. A memory cell area can be made small without increasing wirings more than required.
3. When a cell is made minute, an influence of a cell source impurity diffusion resistance is low, and a cell current can be effectively obtained.
REFERENCES:
patent: 4754320 (1988-06-01), Mizutani et al.
patent: 5150178 (1992-09-01), Mori
patent: 5181090 (1993-01-01), Maruo
patent: 5291046 (1994-03-01), Kumakura
patent: 5656838 (1997-08-01), Shinmori
patent: 59-155968 (1984-09-01), None
patent: 11-087664 (1999-03-01), None
Adams & Wilks
Flynn Nathan J.
Quinto Kevin
Seiko Instruments Inc.
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