Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-07-03
2004-10-19
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000
Reexamination Certificate
active
06806530
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to Korean Patent Application No. 2002-54609, filed on Sep. 10, 2002, which is incorporated herein in its entirety by reference.
1. Technical Field of the Invention
The present invention relates generally to methods for fabricating a non-volatile memory device. The invention further relates to an EEPROM (Electrically Erasable Programmable Read Only Memory) device and methods for fabricating an EEPROM.
2. Background
In general, semiconductor memory devices are divided into two types: (i) RAM (Random Access Memory) devices in which stored information is lost when the power supply is stopped (i.e., volatile memory); and (ii) ROM (Read Only Memory) devices in which stored information is maintained when the power supply is stopped (i.e., non-volatile memory). One example of a non-volatile memory device is an EEPROM device, which electrically erases and programs information.
FIG. 1
schematically illustrates a layout of a unit cell in a conventional EEPROM device. More specifically, as depicted in
FIG. 1
, a unit cell of a conventional EEPROM device comprises active regions
11
that are arranged in a horizontal direction and separated by a predetermined interval. A sense line
13
and word line
15
are disposed perpendicular to the active regions
11
, and are separated from each other by a predetermined distance.
A common source region
17
is arranged in the active regions
11
at the left side of the sense line
13
, and a floating junction region
19
is arranged between the sense line
13
and the word line
15
and under a tunnel region
18
on the active regions
11
. In particular, an N+ ion implantation region
21
is formed under the tunnel region
18
. A drain region
23
is arranged at the right side of the word line
15
, and a bit line contact hole
25
, which is used to connect to a bit line (not shown), is arranged in the drain region
23
.
In addition, during fabrication, field ion implantation masks
27
are arranged in the horizontal direction to be parallel with the active regions
11
, on inactive regions which are separated from the active regions
11
in the horizontal direction by a predetermined distance. As explained below, field ions are implanted in regions of the device in the pattern of the field ion implantation masks
27
. Furthermore, during fabrication, floating gate masks
29
are installed on the sense line
13
to overlap the field ion implantation masks
27
to form floating gates. As explained below, a polysilicon layer which is patterned to form floating gates is etched at the portions corresponding to the floating gate masks
29
so that the floating gates are separated by cell unit. The floating gate masks
29
are installed only on the sense line
13
in order to prevent the word line
15
from being broken.
The conventional EEPROM device of
FIG. 1
is divided into two transistor regions: a memory transistor region comprising the common source region
17
, the floating junction region
19
, the floating gates (not shown), and the sense line
13
; and a selection transistor region comprising the floating junction region
19
, the drain region
23
, and the word line
15
.
FIGS. 2A through 5C
are cross sectional views illustrating a method for fabricating the EEPROM device of FIG.
1
. More specifically,
FIGS. 2A
,
3
A,
4
A, and
5
A are cross sectional views illustrating the EEPROM device of
FIG. 1
along the line Y
1
-Y
1
′.
FIGS. 2B
,
3
B,
4
B, and
5
B are cross sectional views illustrating the EEPROM device of
FIG. 1
along the line Y
2
-Y
2
′.
FIGS. 2C
,
3
C,
4
C, and
5
C are cross sectional views illustrating the EEPROM device of
FIG. 1
along the line X-X′.
Referring to
FIGS. 2A through 2C
, a gate insulating layer
105
and a tunnel insulating layer
107
are formed on a semiconductor substrate
101
having inactive regions
103
as field insulating layers. A first polysilicon layer
109
, which is later doped with impurities, is formed on the gate insulating layer
105
and the tunnel insulating layer
107
.
Thereafter, first photoresist patterns
111
are formed on the first polysilicon layer
109
. The first photoresist patterns
111
are formed by depositing a first photoresist layer on the first polysilicon layer
109
and then exposing and developing the first photoresist layer using a field ion implantation mask
27
(refer to FIG.
1
). The first photoresist patterns
111
are formed by removing the portions of the photoresist that were covered by the field ion implantation masks
27
(i.e., positive resist).
Next, field ions
113
are implanted into regions of the semiconductor substrate
101
exposed by the first photoresist patterns
111
. The field ion implantation process
113
is performed by implanting impurities, for example, boron ions into the portions of the substrate that were masked by the field ion implantation masks
27
.
Referring to
FIGS. 3A through 3C
, the first photoresist patterns
111
are removed. Thereafter, second photoresist patterns
115
are formed on the first polysilicon layer
109
. The second photoresist patterns
115
are formed by depositing a second photoresist layer on the first polysilicon layer
109
, and then exposing and developing the second photoresist layer using the floating gate masks
29
(refer to FIG.
1
).
Next, the first polysilicon layer
109
is etched using the second photoresist patterns
115
as an etch mask to form first polysilicon layer patterns
109
a
. In effect, the first polysilicon layer
109
is etched in regions corresponding to the pattern of the floating gate masks
29
. As shown in
FIG. 1
, the floating gate masks
29
are disposed over the memory transistor region to prevent the word line
15
, which is formed of the first polysilicon layer patterns or the second polysilicon patterns to be formed in a subsequent process, from being broken. As a result, the first polysilicon layer patterns
109
a
are separated by cell unit to become floating gates in the memory transistor region.
Referring to
FIGS. 4A through 4C
, after removing the second photoresist patterns
115
that were used as the etch mask to etch the first polysilicon layer, an insulating layer
117
is deposited over the semiconductor substrate
101
having the first polysilicon layer patterns
109
a
. Typically, the insulating layer
117
is formed of an oxide
itride/oxide (ONO) layer.
Referring to
FIGS. 5A through 5C
, a second polysilicon layer
119
(in which impurities are doped) is formed on the semiconductor substrate
101
having the insulating layer. Thereafter, the second polysilicon layer
119
is etched to form second polysilicon layer patterns
119
a
as shown in FIG.
5
C. The second polysilicon layer patterns
119
a
serve as the gate of the memory transistor region or the selection transistor region.
As described above, in a conventional EEPROM device, the floating gate masks are formed in the memory transistor region as shown in
FIG. 1
in order to prevent the word line from being broken. In addition, only the first polysilicon layer
109
in the memory transistor region is etched (in accordance with the floating gate mask pattern), as shown in
FIGS. 3A through 3C
.
The process for fabrication a conventional EEPROM device as described above uses field ion implantation masks and floating gate masks to form photoresist patterns. However, as shown in
FIG. 1
, for example, these masks are overlapped. Accordingly, it would be desirable to develop a method for fabricating an EEPROM device in which the field ion implantation mask and the floating gate mask are combined into one mask in order to simplify the fabrication process.
SUMMARY OF THE INVENTION
The present invention is directed to EEPROM devices and methods for fabrication EEPROM devices using simplified fabrication processes.
According to one embodiment of the invention, an EEPROM device comprises: a memory transistor including a tunnel insulating layer, first conductive layer patterns, and second conductive l
F. Chau & Associates LLC
Ho Tu-Tu
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