Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-18
2002-04-16
Nguyen, Viet Q. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C365S185010
Reexamination Certificate
active
06373094
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic devices, and more particularly, to an EEPROM cell that may be manufactured using conventional process steps.
BACKGROUND OF THE INVENTION
The manufacture and use of EEPROMs (Electrically Erasable Programmable Read Only Memory) is well developed and understood. EEPROMs provide a very convenient form of nonvolatile memory that can be programmed, erased, and reprogrammed several thousand times.
EEPROM cells are typically formed from a single metal oxide semiconductor (MOS) transistor on a semiconductor substrate. This transistor usually includes a layer of polysilicon associated with the gate-oxide layer of the transistor. This structure forms a capacitor comprised of the polysilicon layer (first plate), gate-oxide layer (dielectric), and substrate (second plate). The basic goal of an EEPROM cell is to provide a mechanism for placing on or removing from the polysilicon layer charge. The presence or absence of charge on the polysilicon layer associated with the gate determines the digital value of the cell, i.e., a “1” or a “0,” respectively.
The placement and removal of the charge from the polysilicon layer requires a source of electrical charge be provided in the vicinity of the polysilicon layer. Several techniques have been previously developed to provide such structures. These include the use of two layers of polysilicon as described in U.S. Pat. No. 4,342,099, issued to Kuo, entitled Electrically Erasable Programmable MNOS Read Only Memory, and U.S. Pat. No. 4,554,643, also issued to Kuo, entitled Electrically Erasable Programmable MNOS Read Only Memory, both of which are assigned to the assignee of the present application. These patents are expressly incorporated by reference for all purposes herein.
Another approach utilizes a single layer of polysilicon with a thin layer of N+ material diffused into the substrate in the polysilicon and gate-oxide region prior to the formation of the polysilicon and gate-oxide layers. The thin layer of charged or doped material below the gate-oxide allows charge to tunnel through the oxide layer and deposit on the polysilicon layer during programming. Because of the tunneling effect, this charge layer is often referred to as the “TUNL” layer. This EEPROM cell has three components, two TUNL capacitors, and an NMOS transistor. One plate of each of the TUNL capacitors and the gate of the NMOS transistor are a blocking piece of polysilicon during the formation of the transistor.
Overall, EEPROM cells have proven to be a very reliable and versatile form of nonvolatile reprogrammable memory. This versatility has contributed to the use of EEPROM cells in devices other than memory devices. For example, EEPROM cells have been used in mixed signal (analog and digital) devices as part of “trimming circuits.” Using EEPROM cells in such devices requires that the cell only be programmed a few times, usually at final test, as opposed to requiring programming capability several thousand times for a standard EEPROM cell used in a memory device.
EEPROM cells used in non-memory devices are typically built on a semiconductor substrate that also contains standard CMOS transistors. Because of the structural differences between standard CMOS transistors and EEPROM cells, additional processing steps are required to form the EEPROM cell and the CMOS transistor on the same substrate. These additional steps may add significant cost and time in fabricating the device, often adding as much as 25% more expense to the circuit's fabrication costs. Faced with ever increasing demands for higher yields, at lower cost, with quicker turnaround times, these additional processing steps required to build an EEPROM cell on a substrate along with standard CMOS transistors may be unacceptable.
SUMMARY OF THE INVENTION
Therefore, a need has arisen for an EEPROM cell and method of manufacture that uses conventional process steps.
In accordance with the present invention, an EEPROM cell formed using conventional process steps is provided that substantially eliminates or reduces disadvantages and problems associated with using EEPROM cells and CMOS transistors on a single wafer.
One aspect of the present invention provides an EEPROM cell formed on a substrate having an outer surface. The cell includes first and second conductive regions in the substrate below the substrate's outer surface, and the first and second conductive regions are laterally displaced from one another by a predetermined distance. The cell also includes an insulating layer outwardly from the outer surface of the substrate positioned so that its edges are substantially in alignment between the first and second conductive regions. The cell further includes a floating gate layer outwardly from the insulating layer and in substantially the same shape as the insulating layer. The cell also includes a diffusion region that extends laterally from at least one of the first and second conductive regions so as to overlap with the insulating layer. The diffusion region provides a source of charge for placement on the floating gate layer when programming the EEPROM cell.
Another aspect of the present invention provides a method for forming an EEPROM cell on a substrate having an outer surface. The method includes forming first and second conductive regions in the substrate below the substrate's outer surface with the first and second conductive regions laterally displaced from one another by a predetermined distance. The method also includes forming an insulating layer outwardly from the outer surface of the substrate that is positioned so that its edges are substantially in alignment between the first and second conductive regions. The method also includes forming a floating gate layer outwardly from the insulating layer and in substantially the same shape as the insulating layer. The present method also includes forming a diffusion region that extends laterally from at least one of the first and second conductive regions so as to overlap with the insulating layer. The diffusion region provides a source of charge for placement on the floating gate layer when programming the EEPROM cell.
Another aspect of the present invention provides an EEPROM cell formed on a substrate having an outer surface. The cell includes a deep conductive region in the substrate below the substrate's outer surface. The cell also includes first and second conductive regions in the substrate below the substrate's outer surface, and the first and second conductive regions are laterally displaced from one another by a predetermined distance. The cell includes an insulating layer outwardly from the outer surface of the substrate positioned so that its edges are substantially in alignment between the first and second conductive regions. The cell further includes a floating gate layer outwardly from the insulating layer and in substantially the same shape as the insulating layer. The deep conductive region provides a source of charge for placement on the floating gate layer when programming the EEPROM cell.
Yet another aspect of the present invention provides a method for forming an EEPROM cell on a substrate having an outer surface. The method includes forming a deep conductive region in the substrate below the substrate's outer surface. The method also includes forming first and second conductive regions in the substrate below the substrate's outer surface with the first and second conductive regions laterally displaced from one another by a predetermined distance. The method further includes forming an insulating layer outwardly from the outer surface of the substrate positioned so that its edges are substantially in alignment between the first and second conductive regions. The method also includes forming a floating gate layer outwardly from the insulating layer and in substantially the same shape as the insulating layer. The deep conductive region provides a source of charge for placement on the floating gate layer when
Chen Wayne T.
Devore Joseph A.
Jordanger Ricky D.
Marshall Andrew
Teggatz Ross E.
Brady III W. James
McLarty Peter K.
Nguyen Viet Q.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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