EEPROM cell with the drain diffusion region self-aligned to the

Details EEPROM cell with the drain diffusion region self-aligned to the EEPROM cell with the drain diffusion region self-aligned to the

1994-03-17

1995-04-04

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257318, H01L 2978

Patent

active

054040370

ABSTRACT:
A method of semiconductor fabrication, in which a single aperture is used to define both a thin oxide tunneling region and a drain diffusion region in a self-aligned fashion, produces a device structure suitable for use in an electrically-erasableread-only memory (EEPROM) cell. A gate oxide is grown, then a photoresist mask is formed having a slit for ion implantation into the drain diffusion region. The oxide within the slit is etched away, and ion implantation forms a drain diffusion region. After the mask is stripped away, a healing furnace cycle removes the implant damage. A thin tunnel oxide layer is grown over the drain diffusion region, and then a polysilicon floating gate is formed so that one edge of this gate intersects a portion of the area of tunnel oxidation so as to form a small region of tunnel oxide under the floating gate. The process sequence then reverts to a conventional MOS flow. The self-aligned drain diffusion region and tunnel oxide region can be used in a variety of EEPROM cell designs. One embodiment involves a double-polysilicon, single-metal process in which three diffusion regions are used to form the EEPROM cell. The second layer of polysilicon overlies the floating gate and forms a control gate word line. The control gate and the floating gate overly the channel between the drain diffusion region and a common source diffusion region. The first layer of polysilicon is also used to form a select gate overlying the channel between the drain diffusion region and a select drain diffusion region. The metal layer provides contact to the select drain diffusion region and forms the bit line.

REFERENCES:
patent: 5273923 (1993-12-01), Chang et al.
C. Kuo et al., An 80 ns 32K EEPROM Using the FETMOS Cell, Journal of Solid-State Circuits vol. SC-17, No. 5, Oct. 1982, pp. 821-827.
T. Y. Chan et al., The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling, Electronics Research Laboratory, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, Calif. 94720 1987, pp. 718-721, (IEDM).
W. S. Johnson et al., THPM 12.6: A 16Kb Electrically Erasable Nonvolative Memory, ISSCC 80/Thursday, Feb. 14, 1980, 1980 IEEE International Solid-State Circuits Conference, pp. 152-153, Digest of Technical Papers.

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