Deep trench with enhanced sidewall surface area

Deep trench-buried layer array and integrated device...

Deep-trench capacitor with hemispherical grain silicon...

Defect induced buried oxide (DIBOX) for throughput SOI

Defect-free source/drain extensions for MOSFETS having...

Delta doped and counter doped dynamic threshold voltage MOSFET f

Demultiplexers using transistors for accessing memory cell...

Dense arrays and charge storage devices

Dense backplane cell for configurable logic

Dense multi-gated device design

Dense pitch bulk FinFET process by selective EPI and etch

Dense semiconductor fuse array

Dense SOI flash memory array structure

Dense SOI programmable logic array structure

Dense SRAM cells with selective SOI

Dense trench MOSFET with decreased etch sensitivity to...

Dense vertical programmable read only memory cell structure and

Dense vertical programmable read only memory cell structures and

Dense vertical programmable read only memory cell structures and

Densely patterned silicon-on-insulator (SOI) region on a wafer