Dense vertical programmable read only memory cell structure and

Details Dense vertical programmable read only memory cell structure and Dense vertical programmable read only memory cell structure and

1990-12-18

1994-08-30

Ngo, Ngan Van

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257319, 257320, 365900, H01L 2968, H01L 2978

Patent

active

053430638

ABSTRACT:
A memory array of PROM, EPROM or EEPROM cells has each cell formed in a trench of a thick oxide layer deposited on a silicon substrate, in a manner that a significant portion of opposing areas of the floating gate and control gate of each cell which provide capacitive coupling between them are formed vertically. This allows the density of the array to be increased since the amount of semiconductor substrate area occupied by each cell is decreased without having to sacrifice the amount or quality of the capacitive coupling. Further, a technique of forming capacitive coupling between the floating gate and an erase gate in a flash EEPROM array cell with improved endurance is disclosed.

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