Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-02-22
2002-08-06
Dang, Trung (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S413000, C438S478000, C438S479000, C257S296000, C257S347000
Reexamination Certificate
active
06429488
ABSTRACT:
TECHNICAL FIELD
The present invention relates, in general, to the process of making a semiconductor device and, more specifically, to a process of making a semiconductor device having a silicon-on-insulator (SOI) region and a non-SOI (bulk) region.
BACKGROUND OF THE INVENTION
A silicon-on-insulator (SOI) structure is formed when a buried insulating layer electrically isolates a silicon layer from a silicon substrate. The SOI structure does not usually occupy the entire surface of the silicon substrate. Such a selective SOI structure is disclosed by Tanigawa in U.S. Pat. No. 5,740,099, issued Apr. 14, 1998. There shown is an integrated circuit fabricated partially on the SOI structure and partially on the silicon substrate. The circuit area assigned to the SOI structure is referred to as the SOI region, and the circuit area assigned outside the SOI structure is referred to as the bulk region. Tanigawa teaches building regions of SOI and bulk silicon on a substrate and fabricating different types of circuits in each region. Tanigawa uses a patterned ion implant technique to build the different regions. For example, a very high dose of oxygen ions is implanted deep within the silicon at sufficient energy to form the buried layer of silicon dioxide.
Tanigawa's method has several drawbacks. A high dose of oxygen is required to form a sharp Si/SiO
2
interface and high energy of implantation is required to achieve the buried layer. This method is also known to cause defects at all of the patterned edge regions and usually results in a non-planar structure because oxidation causes expansion of the SOI portion of the wafer.
Another publication, titled “Process for Fabrication of Very Thin Epitaxial Silicon Films Over Insulating Layers,” IBM Technical Disclosure Bulletin, Volume 35, No. 2, pages 247-49 (July 1992) (author unknown), teaches the use of selective epitaxial growth of silicon to grow regions of SOI on a wafer. As shown in
FIG. 1
a
of the publication (also
FIG. 1
a
of this specification), two mask levels are used to create structure
40
which includes silicon substrate
42
and insulating oxide layer
44
. Oxide opening
48
is formed from a first masking process, and the height of the center portion of the oxide layer, island
50
, is controlled by a second masking process.
Next, epitaxial silicon
46
is grown selectively as shown in
FIG. 1
b
. A chemical-mechanical polish is used to remove the excess epitaxial material. Insulating oxide layer
44
acts as a reference point for the chemical-mechanical polish, so that the remaining epitaxial silicon ends up flush with the oxide layer, as shown in
FIG. 1
c
. In this manner, the SOI region is formed to make the silicon island
50
completely isolated from the insulating oxide layer
44
.
This process, known as epitaxial lateral overgrowth (ELO), has its drawbacks. The area of SOI formed may only be up to approximately 10 microns thick. The size and quality of silicon is limited when the SOI formed is wider then 10 microns in regions
52
of
FIG. 1
c
. Consequently, the amount of SOI devices on a wafer is also limited.
It is necessary to combine both logic and dynamic random access memory (DRAM) circuitry, for example, in the same chip in order to make a high-performance microprocessor. A SOI structure is one of the possible candidates for fabricating a high-performance microprocessor. It is difficult to make high-performance DRAM cells on SOI, however, because of lack of substrate connection for the DRAM pass transistors. The lack of substrate connection results from the inability to grow SOI that is sufficiently wide to allow fabrication of many DRAM cells on a single island of SOI. Because many islands of SOI need to be grown, a common substrate is lacking. Lack of a common substrate may also cause floating body effects and severe cell leakages, thereby degrading DRAM performance.
In U.S. Pat. No. 5,399,507 issued to Sun on Mar. 21, 1995, a process is disclosed for fabricating a mixed thin film and bulk semiconductor substrate. A thin film over the SOI structure is masked and etched to expose the underlying bulk substrate. An epitaxial layer is then grown to build the exposed bulk portion to form the mixed substrate. Before growing the epitaxial layer, however, Sun teaches (1) that a dielectric layer be deposited over the entire substrate, and (2) that the dielectric layer be selectively etched to form sidewall spacers in order to separate the SOI region from the bulk region in the substrate.
After completing the aforementioned two steps, Sun grows the epitaxial layer over the bulk region. Finally, Sun forms a shallow trench isolation (STI) region within the SOI region, and another STI region within the bulk region. Thus, Sun teaches how to form a mixed SOI region and a bulk region on a single substrate. The drawback in Sun's process is that many steps are required to separate the two regions. Specifically, Sun requires the formation of the sidewall spacers, in addition to the conventional step of forming the STI regions. Moreover, as shown in
FIG. 11
of Sun's disclosure, STI region
54
is formed over the bulk region and STI region
52
is formed over the SOI region. Both STIs are formed adjacent to wall spacer
46
. Forming the trenches for the STIs is difficult because the spacer abuts the STIs.
The deficiencies of conventional processes in making SOI and bulk regions on the same wafer, and the difficulties in making high-quality, densely patterned SOI regions suitable for microprocessors, show that a need still exists for a process which can make densely patterned SOI for merged logic and DRAM circuitry, or for other types of circuitry.
SUMMARY OF THE INVENTION
To meet this and other needs, and in view of its purposes, the present invention provides a process for making densely patterned SOI on a wafer. In one embodiment, the process includes making a SOI region and a bulk region in a semiconductor device. The process includes providing a SOI structure having a thin silicon layer, a buried insulating oxide layer underlying the thin silicon layer, and a silicon substrate underlying the buried insulating oxide layer. Next, a nitride layer is deposited on top of the SOI structure. The SOI structure is exposed by selectively etching portions of the nitride layer. The portion of the nitride layer which is not etched forms the SOI region. The silicon substrate is exposed by selectively etching the remaining portion of the exposed SOI structure. An epitaxial layer is grown on top of the exposed silicon substrate to form the bulk region. The nitride portion above the SOI structure is finally removed. A logic circuit may be formed above the SOI region and a DRAM circuit may be formed above the bulk region.
It is understood that the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
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Process for Fabrication of Very T
Leobandung Effendi
Sadana Devendra K.
Schepis Dominic J.
Shahidi Ghavam G.
Abate Esq. Joseph P.
Dang Trung
Ratner & Prestia
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