Dense backplane cell for configurable logic

Details Dense backplane cell for configurable logic Dense backplane cell for configurable logic

2001-08-30

2003-03-18

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000, C257S391000, C257S392000

Reexamination Certificate

active

06534819

ABSTRACT:

BACKGROUND
A widely used class of semiconductor integrated circuits include configurable circuits such as field programmable gate arrays, complex programmable logic devices, etc. These are gate arrays that can be configured electronically in order to achieve one or more desired logic functions. The architecture, based on the size of blocks and their partitioning, allows implementations that vary in speed, density, power and functionality. These configurable arrays can quicky implement complex logic designs that are required for computers, networks, and other complex electronic devices and systems. One example of a configurable logic array is found in U.S. Pat. No. 6,063,686, whose disclosure is incorporated by reference. Configurable logic devices often substitute for more expensive custom logic devices and application specific integrated circuits. Configurable logic and memory devices often included excess or unused cells. Those extra or unused cells have been the basis of work that allows defect-tolerant computing and dynamic reconfigurability.
Most common implementations suffer from the need of a large number of devices to implement simple programmable functions. This invention describes a cell structure that is denser by as much as a factor of 10 compared to the SRAM-based structures. The dense structure allows scaling to significantly smaller dimensions in feature size, allows for a common technology for logic and memory structure, is non-volatile, scales to smaller dimensions than conventional logic cells, and provides a path through which semiconductor nanostructures could be implemented with defect tolerance and configurability. Dense memory structures are possible with backgate techniques. See U.S. Pat. No. 6,248,626 whose entire disclosure is incorporated by reference thereto. However, such techniques have not been applied to programmable logic devices.
SUMMARY
The invention provides a programmable logic integrated circuit with a plurality of programmable logic cells. Each programmable logic cell has a support substrate covered with a first insulating layer and a backgate on the first insulating layer. The backgate is conductive and may be either doped polysilicon or a suitable metal. A second insulating layer covers the backgate and insulates it from a superior device layer. The device layer is a layer of monocrystalline semiconductor material, such as silicon. In each cell there are two transistors. One transistor provides access to the other transistor. The other transistor is programmed by storing charge on the backgate.
The programmable logic integrated circuit may be combined with memory cells of similar structure. The programmed cells are non-volatile and retain their programmed states, on or off, without external power. The integrated circuit may include a plurality of surplus logic cells so that the integrated circuit can use one or more of the surplus cells if one or more of the used cells becomes defective or inoperative.
The architecture of the circuit includes programming lines coupled to programming transistors and to the gates of the transistor cells. The backgate extends beneath the respective channels of the transistors or each cell.
The invention is flexible and may be used to program one device to perform multiple logic function.


REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 5437762 (1995-08-01), Ochia et al.
patent: 5712208 (1998-01-01), Tseng et al.
patent: 5726087 (1998-03-01), Tseng et al.
patent: 5909627 (1999-06-01), Egloff
patent: 6063686 (2000-05-01), Masuda et al.
patent: 6088260 (2000-07-01), Choi
patent: 6103599 (2000-08-01), Henley et al.
patent: 6133602 (2000-10-01), Shrivastava et al.
patent: 6248626 (2001-06-01), Kumar et al.
patent: 6351176 (2002-02-01), Houston

Affiliated with

Also associated with

Rating

Dense backplane cell for configurable logic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dense backplane cell for configurable logic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dense backplane cell for configurable logic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3034628