Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-29
2003-07-29
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000, C257S374000, C257S378000, C257S396000, C257S511000, C257S525000
Reexamination Certificate
active
06600199
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming integrated circuit devices that improves latchup tolerance while also providing improved noise isolation.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density and device performance in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced while increasing the performance of the devices.
The push for ever increasing performance is particularly strong in electronic devices where digital and analog components are formed and must operate together without interference. Unfortunately, there are conflicting design goals that come into play when both analog and digital devices are formed together.
For example, one important issue in analog devices is noise. Noise can determinately effect analog devices in a myriad of ways. As such, it is generally preferable to form these analog devices in way that minimizes the impact of noise on those devices. For example, in bipolar junction transistor technology it is generally preferable to form the devices on p− wafer to maximize the noise tolerance of the devices. While this design choice improves the noise tolerance of the analog bipolar transistors, it has detrimental effects on the digital portions of device.
In particular, using a p− wafer reduces the latchup tolerance of the BiCMOS, CMOS and other elements of the digital devices. Latchup is a well known problem caused by unwanted transistor action between elements of the integrated circuit. This unwanted transistor action can be triggered by a wide variety of events, and can cause the semiconductor device to fail. Latch-up is generally caused by the close proximity of n-channel and p-channel devices in modern CMOS devices.
Thus, for digital devices, it is generally preferable to use a p+ wafer or a p+ buried layer to improve the latchup tolerance of the devices. While a p+ buried layer will serve to increase latchup tolerance, it will also negatively effect the noise tolerance of the bipolar transistors used in the analog devices. Additionally, when buried layers are formed through bipolar transistors, the resulting transistors suffer from increased subcollector-to-substrate capacitance. This limits the operational frequency of the bipolar transistor.
Designers of mixed analog and digital devices have thus been forced to choose between improving noise tolerance or latchup tolerance. Thus, there is currently no effective way to maximize the noise tolerance of analog devices while also maximizing the latchup tolerance of digital devices in mixed analog/digital environments. Without an improved method and structure for forming mixed analog/digital devices, the performance reliability of these devices will continue to be compromised.
DISCLOSURE OF INVENTION
Accordingly, the present invention provides a unique device structure and method that provides increased noise tolerance and latchup immunity in integrated circuit devices. The preferred embodiment of the present invention provides a buried layer that improves the latch up immunity of digital devices while providing isolation structures that provide noise isolation for both the digital and analog devices. The buried layer of the preferred embodiment is formed to reside within or below the subcollector region in the transistor. When formed within the buried layer doping is overwhelmed by the subcollector doping in the transistor region. Additionally, in the preferred embodiment the subcollector is isolated from buried layer outside the transistor region by deep isolation trenches formed at the edges of the subcollector. By forming the buried layer within the subcollector in the transistor region and forming deep isolation trenches at the edges of the subcollector, subcollector leakage, capacitance and noise transmission that would otherwise result from the buried layer is reduced. In an additional embodiment, an array of deep isolation trenches provides increased isolation between devices where needed. Thus, the preferred embodiment of the present invention provides an integrated circuit structure and method that provides improved latchup immunity while also providing improved noise tolerance.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.
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Johnson Robb A.
Lanzerotti Louis D.
St. Onge Stephen A.
Voldman Steven H.
Henkler Richard A.
International Business Machines - Corporation
Lee Eddie
Schmeiser Olsen & Watts
Warren Matthew E.
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