Demultiplexers using transistors for accessing memory cell...

Details Demultiplexers using transistors for accessing memory cell... Demultiplexers using transistors for accessing memory cell...

2008-05-05

2010-11-09

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S204000, C257S274000

Reexamination Certificate

active

07829926

ABSTRACT:
A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2Nsemiconductor regions which are parallel to one another and run in a first direction; (c) first N gate electrode lines, which (i) run in a second direction which is perpendicular to the first direction, (ii) are electrically insulated from the 2Nsemiconductor regions, and (iii) are disposed between the first plurality of memory cells and the contact region; (d) a contact region; (e) a first plurality of memory cells. An intersection transistor exists at each of intersections between the first N gate electrode lines and the 2Nsemiconductor regions. In response to pre-specified voltage potentials being applied to the contact region and the first N gate electrode lines, memory cells of the first plurality of memory cells disposed on only one of the 2Nsemiconductor regions are selected.

REFERENCES:
patent: 5933366 (1999-08-01), Yoshikawa
patent: 6256767 (2001-07-01), Kuekes et al.
patent: 6385075 (2002-05-01), Taussig et al.
patent: 6478231 (2002-11-01), Taussig
patent: 6854092 (2005-02-01), Hogg
patent: 7075844 (2006-07-01), Pagliato et al.
patent: 7554861 (2009-06-01), Vimercati et al.
patent: 7562269 (2009-07-01), Yoshida et al.
patent: 2004/0113139 (2004-06-01), DeHon et al.
patent: 2005/0006671 (2005-01-01), Heath et al.
patent: 2005/0055387 (2005-03-01), Kuekes et al.
patent: 2005/0193356 (2005-09-01), Kuekes et al.
patent: 2006/0214683 (2006-09-01), DeHon
patent: 2007/0130488 (2007-06-01), Nakashima et al.
patent: 2008/0013378 (2008-01-01), Crippa et al.
Hogg et al.; Assembling Nanoscale Circuits with Randomized Connections; Sep. 8, 2005; 20 pages.
Snider et al.; Crossbar Demultiplexers for Nanoelectronics Based on n-Hot Codes; IEEE Transactions on Nanotechnology, vol. 4, No. 2; Mar. 2005; 1536-125X; pp. 249-254.
Zhong et al.; Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems; www.sciencemag.org; Science, vol. 302; Nov. 2003; pp. 1377-1379.
Strukov et al.; CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices; Institute of Physics Publishing; Nanotechnology 16 (2005); doi:10.1088/0957-4484/16/6/045; pp. 888-900.
Beckman et al.; Bridging Dimensions: Demultiplexing Ultrahigh-Density Nanowire Circuits; www.sciencemag.org; Science, vol. 310, Oct. 21, 2005; pp. 465-468.
Ma et al.; Afterlife for Silicon: CMOL Circuits Architectures; Email: klikharev@notes.cc.sunysb.edu; 4 pages.
Dehon et al.; Nonphotolithographic Nanoscale Memory Density Prospects; IEEE Transactions on Nanotechnology, vol. 4, No. 2; Mar. 2005; pp. 215-228.

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