Circuit having a controllable slew rate
Circuit including DRAM and voltage regulator, and method of incr
Circuit including DRAM and voltage regulator, and method of incr
Circuit of reducing transmission delay for synchronous DRAM
Circuit pre-charge to sense a memory line
Circuit structure and method for stress testing of bit lines
Circuit structure having distributed registers with self-timed r
Circuit technique for column redundancy fuse latches
Circuit that prevents illegal transformation of data in a...
Circuit using a shared delay locked loop (DLL) and method...
Circuit which provides power on reset disable during a test mode
Circuit with a memory array and a reference level generator...
Circuit, system and method for executing a refresh in an...
Circuital structure for reading data in a non-volatile...
Circuitry and method for discharging a drain of a cell of a non-
Circuitry and method for indicating a memory
Circuitry and method for programming and erasing a non-volatile
Circuitry and methodology to test single bit failures of integra
Circuitry and methods for dynamically sensing of data in a stati
Circuitry and methods for efficient FIFO memory