Circuit with a memory array and a reference level generator...

Details Circuit with a memory array and a reference level generator... Circuit with a memory array and a reference level generator...

2006-01-05

2011-12-20

Hidalgo, Fernando N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S185030, C365S185050, C365S185180, C365S185200, C365S185210, C365S189150, C365S189070, C365S230060, C365S242000

Reexamination Certificate

active

08081523

ABSTRACT:
A circuit comprises an array of memory cells (10). A plurality of sensing circuits (20), are coupled to the output (14) of respective memory cells (10), for comparing the output signal of the respective one of the memory cells (10) with a reference signal to form a data signal from the output signal from the respective one of the memory cells (10). A reference generator circuit (24, 26) forms the reference signal from a sum wherein each respective one of the memory cells (10) of the addressed group contributes a contribution that is a function of the output signal of the respective one of the memory cells (10). The contributions are equalized for output signal values at more than a saturating distance above the reference signal, and the contributions are equalized for output signal values at more than the saturating distance below the reference signal. In case of storage of multi-level data in the cells the distances from the central level to the saturation levels above and below the reference level are mutually different, with a ratio that corresponds to a ratio of the counts of cells that have been programmed to respective levels.

REFERENCES:
patent: 6222762 (2001-04-01), Guterman et al.
patent: 7187592 (2007-03-01), Guterman et al.
patent: 7203112 (2007-04-01), Liaw
patent: 2003/0031059 (2003-02-01), Endo et al.
patent: 2004/0062116 (2004-04-01), Takano et al.

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