Circuit structure having distributed registers with self-timed r

Details Circuit structure having distributed registers with self-timed r Circuit structure having distributed registers with self-timed r

1992-11-23

1995-04-18

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

365210, 36523006, 365194, 36518911, G11C 700, G11C 800

Patent

active

054084369

ABSTRACT:
The circuit structure comprises a series of storage units, a data bus, an address bus, a line for a reading/writing signal, a precharge logic suitable for precharging the address bus with a precharge address and a precharge sensor suitable for enabling the operation of address decoders of the storage units with a given delay with respect to the end of the precharge. The structure also comprises a flip-flop for controlling the address buses and the precharge logic as well as a delay circuit capable of producing a stop-writing signal with a delay calculated on the basis of the time necessary for the writing of a datum in a storage register of the storage units.

REFERENCES:
patent: 4551821 (1985-11-01), Yokouchi et al.
patent: 4829475 (1989-05-01), Ward et al.
patent: 5029135 (1991-07-01), Okubo
patent: 5062082 (1991-10-01), Choi
patent: 5084839 (1992-01-01), Young
D. A. Kummer et al. Delayed I/O Read/Write Circuit IBM Technical Disclosure Bulletin vol. 26 No. 12 May 1984, pp. 6364 6365.
National Semiconductor Corporation, Santa Clara, Calif., "Logic Databook, vol. II", 1984, pp. 4-208-4-209.

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