Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-05-23
2003-08-12
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C326S083000, C326S086000, C326S088000
Reexamination Certificate
active
06606271
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to integrated circuits and, more particularly, to output or interface circuits driving output signals in which the slew rate must be controlled to meet customer or industry specifications.
2. Description of the Background
There are many types of output circuits. One type of output circuit, drive circuits, or drivers as they are commonly called, are used in a variety of applications. Typically, the driver acts as an interface between a logic circuit or other circuitry where signals are being manipulated at very low levels and circuits or loads which require high signal levels or large current levels. For example, drivers are found in various types of memory devices as the interface between the internals of the memory device and the external circuitry—microprocessor, etc. In such an environment, the driver is typically used to drive the data pad to a first voltage to represent a logic level 1 and a second voltage to represent a logic level 0. The driver typically must source sufficient current to enable signals available at the data pads to travel significant lengths along buses or to be sensed by other types of loads.
Prior art drive circuits typically utilize a pair of output drive transistors designed to operate in a complementary fashion. For example, the data pad may be connected to the first voltage through an n-type transistor and connected to the second voltage through a p-type transistor. When one of the transistors is on, the other transistor is off. In modem circuits, both transistors may be off to allow the data pad to receive data.
When designing drivers, it is necessary to insure that the transistors turn off as quickly as possible so as to avoid the situation where both transistors are on. If both transistors are on simultaneously, power will be wasted by current flowing through both transistors to ground or a negative voltage source. Such currents are referred to as “crowbar currents”. Also, because of high operating speeds, it is necessary for the transistors to rapidly change state.
The rate at which an output transistor, the output of an amplifier, or the output of a circuit follows a change in state of an input signal is referred to as the slew rate. As illustrated in
FIG. 1
, if a step pulse is input to, for example, an amplifier, then the output should ideally be a step pulse as illustrated by the dotted line in FIG.
1
. However, there is some finite rise time associated with the output signal, and that rise time or response rate is referred to as the slew rate. The slew rate is the slope of the line and is thus represented by voltage over time.
Another phenomenon that occurs that prevents the output signal from being a perfect step pulse occurs as the result of the output signal overshooting the final voltage value. After overshooting the final voltage value, the output signal approaches the final voltage either exponentially or with some damped ringing. The settling time is defined as the time between the edge of the applied step function and the point where the circuit output settles to within some stated percentage of the target voltage value. Slew rate and settling time present the circuit designer with competing design criteria. For example, a fast slew rate may actually increase settling time because a fast slew rate may result in a substantial overshooting of the desired final voltage value. Therefore, there is often a tradeoff between slew rate and settling time. In many applications, industry or individual consumers will set values for slew rate, settling time, as well as other parameters.
U.S. Pat. No. 5,838,191 entitled Bias Circuit for Switched Capacitor Applications (“the '191 patent”) illustrates an example of a circuit that compensates for temperature and process variations by maintaining a constant settling time of CMOS operational amplifiers. An adaptive bias circuit allows a dynamic tradeoff between the slew rate and the gain bandwidth product which allows the output of the operational amplifier to settle within a certain predetermined precision. The '191 patent discloses a current source providing the same current to a pair of transistors having different effective current densities. A resistor is coupled between the pair of transistors while from one end of the resistor, a constant bias current is drawn. In that manner, the voltage difference across the resistor effectively indicates the change in the transconductance of the pair of transistors with respect to temperature and process variations.
U.S. Pat. No. 5,619,147, entitled CMOS Buffer with Controlled Slew Rate and U.S. Pat. No. 5,877,643 entitled CMOS Buffer with Controlled Slew Rate disclose a method and apparatus for a CMOS buffer circuit having a controlled slew rate at the output using no additional standby power to achieve the slew rate. A feedback path from the output is coupled to transistors comprising a differential pair. The transistors are further coupled to a capacitance. The charge rate of the capacitance and the size choices of the transistors are used with the feedback path to control the high-to-low and low-to-high transition rate of the output.
U.S. Pat. No. 6,163,169 is entitled CMOS Tri-State Control Circuit for a Bidirectional I/O with Slew Rate Control (the '169 patent). The '169 patent discloses a digital circuit which pulls up an output node using an NFET device. The digital circuit is part of a CMOS pre-driver having balanced delays for coming out of a tri-state mode and for data mode operation.
U.S. Pat. No. 6,172,522 is entitled Slew Rate Controlled Pre-driver Circuit (the '522 patent). In the '522 patent, a digital CMOS pre-driver circuit pulls an output node up and down with accurately controlled rise and fall times in the threshold region. Resistors independently set rise and fall slew rates while additional CMOS devices initially charge and discharge an output node. The additional devices turn off before the output reaches the threshold region.
U.S. Pat. No. 5,296,766 is entitled CMOS Circuit with Crow bar Limiting Function (the '766 patent). The '766 patent discloses a CMOS amplifier circuit in which crow bar current is limited during a transition state where one transistor is being turned on and another transistor is being turned off.
Despite a number of circuits directed to this problem, the need still exists for an output or interface circuit having an adjustable slew rate, while minimizing or eliminating crow bar currents, and implemented with a minimal parts count.
SUMMARY OF THE PRESENT INVENTION
The present invention is directed to a circuit for producing an output signal at an output thereof in response to an input signal at an input thereof. The circuit may be embodied, for example, in a driver circuit. The present invention, in one embodiment, is comprised of a first switch for connecting the output to a first voltage source and a second switch for connecting the output to a second voltage source. A first control switch is provided for turning off the first switch in response to the logic level of the input signal while a second control switch is provided for turning off the second switch in response to the logic level of the input signal. An integrator is responsive to the input signal for turning on one of the first and second switches depending on the logic level of the input signal.
The present invention is also directed to a method of operating an output circuit of the type having first and second switches connecting first and second voltage sources, respectively, to an output in response to the logic levels of an input signal. The method is comprised of the steps of:
turning off the one of the first and second switches which is on in response to a change in logic level of the input signal;
integrating the input signal; and
turning on the one of the first and second switches which was previously off in response to the integrated input signal.
The present invention, when implemented in CMOS circuitry, provid
Mircron Technology, Inc.
Nguyen Van Thu
Thorp Reed & Armstrong LLP
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