Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-09-15
2002-06-04
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S189020
Reexamination Certificate
active
06400631
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory, and specifically to a method and circuit for refresh of a volatile memory.
2. Description of the Related Art
A DRAM, or Dynamic Random Access Memory, contains a memory cell array having a plurality of individual memory cells arranged as a matrix of rows and columns. Each memory cell is coupled to one of a plurality of bit lines and to one of a plurality of word lines. This matrix is usually subdivided into a number of banks. When a DRAM delivers data from a bank, an entire row of data from the memory cells is moved from the matrix into an array of sense amplifiers, a process known as “opening a page”. Subsequently, the sense amplifiers transfer a subset of the data to the DRAM device pins. Once the data has been delivered to the pins, the sense amplifiers restore the data to the memory cell, and the page can be “closed”.
Each memory cell in a DRAM is constructed from a single transistor and a single capacitor and is called dynamic because its data decays and becomes invalid due to various leakage current paths to surrounding cells and to the substrate. Therefore, to keep the data in the cells valid, each memory cell is periodically refreshed. Data in the DRAM cell array is refreshed every time it is read out of the cell array into the sense amplifiers and subsequently rewritten into the cells.
The agent that reads data out of DRAM and writes data into DRAM is known as a memory controller or DRAM controller. This memory controller is responsible for opening and closing pages, reading and writing data, and for periodically performing refresh maintenance operations on the memory cell array. Every row of the memory array needs to be refreshed before the data in the row decays to an invalid state. The typical refresh time period for one row of the DRAM array is a few microseconds. In addition, memory controllers are often designed so that they leave pages in the open state for prolonged periods of time in order to enhance memory system performance. However, since the sense amplifiers are used for the refresh operation, a fundamental conflict arises between convenient execution of refresh requests and a high-performance paging policy.
This conflict has been resolved in a few ways. One current solution is closing open pages that interfere with necessary refresh operations. Another existing solution is delaying refresh operations if there is an interference with pages that are currently open. The first policy degrades memory access operations in favor of timely refresh. The second policy also addresses the conflict, but does not fully utilize the bandwidth of the DRAM interface because of the intentional delay of the refresh operations. Yet another existing solution, depicted in
FIG. 1
, is generating a register for each memory bank and sense amplifier pair for storing the contents of the sense amplifier into the register. However, the resulting memory design is extremely inefficient due to the large number of transistors needed to generate a register for each memory bank and sense amplifier pair.
REFERENCES:
patent: 4829484 (1989-05-01), Arimoto et al.
patent: 4979145 (1990-12-01), Remington et al.
patent: 5305274 (1994-04-01), Proebsting
patent: 5659515 (1997-08-01), Matsuo et al.
Dodd Jim M.
Williams Michael W.
Hoang Huan
Intel Corporation
Nesheiwat Michael
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