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Selecting circuit for a memory operating mode

Static information storage and retrieval – Read/write circuit – Having fuse element
Patent

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Selection method of bit line redundancy repair and apparatus...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Selective address space refresh mode

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Selective application of program inhibit schemes in...

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Selective application of voltages for testing storage cells in s

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Selective application of voltages for testing storage cells in s

Static information storage and retrieval – Read/write circuit – Testing
Patent

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Selective automatic precharge of dynamic random access...

Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate

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Selective bank refresh

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Selective bank refresh

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Selective bit line recovery in a memory array

Static information storage and retrieval – Read/write circuit – For complementary information
Patent

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Selective bulk write operation

Static information storage and retrieval – Read/write circuit
Patent

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Selective forwarding of a strobe based on a predetermined...

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Selective memory refresh circuit and method

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Selective program voltage ramp rates in non-volatile memory

Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate

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Selectively decoupled I/O latch

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent

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Self adjusting delay circuit and method for compensating sense a

Static information storage and retrieval – Read/write circuit – Differential sensing
Patent

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Self adjusting pre-charge delay in memory circuits and methods f

Static information storage and retrieval – Read/write circuit – Differential sensing
Patent

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Self boosted wordline

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent

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Self burn-in circuit for semiconductor memory

Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate

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Self calibrating register for source synchronous clocking...

Static information storage and retrieval – Read/write circuit – With shift register
Reexamination Certificate

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