Self boosted wordline

Details Self boosted wordline Self boosted wordline

1998-12-18

2000-02-29

Tran, Andrew Q.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36518906, 365203, 365204, 36523006, G11C 700

Patent

active

06031768&

ABSTRACT:
This invention is a method for boosting the voltage level of a wordline in a DRAM having bitlines, sense amplifiers, isolation devices, bitline loads, an X decoder device and a Y select device. In the preferred method, when the wordline level reaches VDD, the decoder is disabled causing the wordline to stay at the VDD level. The sensing amplifier is also caused to be isolated so as to allow the wordline voltage to track the bitline voltage through capacitive coupling across the access MOSFET of the memory cell being read or written to. As a result, the wordline voltage is increased to a supervoltage as the bitline voltage increases. After the supervoltage is reached on the wordline, the sensing amplifier is connected causing feedback from the amplifier to drive the wordline voltage toward the VDD level and the disabled bit toward GND during this time. At the end of the wordline clock signal, the voltage is at GND and each of the bitlines are returned to their neutral mid-voltage level.

REFERENCES:
patent: 5835438 (1998-11-01), Wu et al.
patent: 5923596 (1999-07-01), Wu et al.
patent: 5946264 (1999-08-01), McClure
patent: 5949720 (1999-09-01), Brady

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