Static information storage and retrieval – Read/write circuit – Testing
Patent
1986-11-24
1989-06-13
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Testing
365226, 36518909, 307296R, G11C 700, G11C 1142
Patent
active
048398659
ABSTRACT:
A dynamic RAM is provided with a plurality of 1-MOSFET memory cells, each having a storage capacitor and a switching MOSFET coupled to one electrode of the storage capacitor. The other electrode of each of the storage capacitors is coupled to a switching circuit which controls the voltage which is applied to the capacitor. The switching circuit is, in turn, coupled to both a voltage generating circuit (which preferably provides a voltage of 1/2 Vcc) and a voltage supply circuit which is set to provide predetermined test voltages. Thus, by operating the switching circuit, a voltage of 1/2 Vcc can be applied to the memory cell capacitors during normal operation of the dynamic RAM, and the predetermined test voltages can be applied to the memory cell capacitors during a testing operation.
REFERENCES:
patent: 4418403 (1983-11-01), O'Toole et al.
patent: 4519076 (1985-05-01), Priel et al.
patent: 4527254 (1985-07-01), Ryan et al.
patent: 4549101 (1985-10-01), Sood
patent: 4616143 (1986-10-01), Miyamoto
patent: 4638460 (1987-01-01), Matsumoto
patent: 4680762 (1987-07-01), Hardee et al.
Nikkei Electrnics Feb. 11, 1985 pp. 243-263.
Kawamoto Hiroshi
Sato Katsuyuki
Yanagisawa Kazumasa
Bowler Alyssa H.
Hecker Stuart N.
Hitachi , Ltd.
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