Static information storage and retrieval – Read/write circuit – With shift register
Reexamination Certificate
2001-12-05
2003-12-16
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
With shift register
C365S194000, C365S233100
Reexamination Certificate
active
06665218
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to source synchronous input/output systems and, more particularly, to techniques for increasing the bandwidth of such systems.
BACKGROUND OF THE INVENTION
A key parameter in limiting the performance of modern computer and network systems is the speed at which data can be reliably transferred between system components. As these systems become faster and faster, it becomes more and more important to increase input/output (I/O) rates. The particular techniques used to address this issue depend in large part upon the transmission scheme.
In one such scheme, source synchronous I/O for parallel bus systems, data rates can be greatly increased when source clock and source data have a fixed, known relationship to each other. In source synchronous I/O systems, the clock signal generated in the transmitting device is sent to the receiving device along with the data signal. The data signal is transmitted in synchronization with the clock and historically was only allowed to transition on either the rising or falling edge of the clock. However, in the more recently developed double data rate (DDR) systems, one bit of data is transmitted on each rising edge of the clock and one bit on each falling edge.
Inherent fixed system mismatches, such as board trace length differences, package trace length differences, on-chip clock routing differences, clock skew, etc. are generally minimized in an attempt to increase I/O data rates. However, in these parallel transmission systems some fixed mismatch always remains between the various input/output parallel paths with an associated limit in attainable data rates. In addition, processing variations can cause changes in clock timing, data bit transition levels, and other rate related parameters.
Other time variant mismatches can also occur. These mismatches might be caused by environmental changes, device parameter drifts, as well as other causes. One particularly important environmental parameter for which a change could result in additional timing mismatches, device parameter shifts, and other changes is temperature. Supply voltage differences from system to system, between transmitting and receiving device, between receiving devices, as well as shifts over time can also result in mismatches. Degradation of device parameters, as for example MOSFET threshold voltage, which can occur over time can also result in mismatches by causing various switching devices to transition at different signal levels. These items can result in further small phase shifts of the received data signal with respect to the clock signal with subsequent decrease in data transmission rate. The reduction in reliable data transmission rate is due to the fact that the switching rate must permit the bit values on all bit-lines to reach stable values during each half clock cycle.
Thus, there is a need for a device which increases source synchronous I/O data rates by counteracting the inherent sources of system mismatches.
SUMMARY OF THE INVENTION
In representative embodiments, self calibrating registers which can increase source synchronous input/output (I/O) data rates by counteracting the inherent systematic sources of system mismatch are disclosed. Systematic sources of system mismatch between bit-line paths and devices, as for example printed circuit board path lengths, package trace lengths, on-chip clock routing, clock skew, device turn-on voltages, etc. are balanced out with respect to a reference clock signal by controlled delays of the data signals. Earlier techniques for reducing these mismatches have done so during the design stage and have had only limited success.
Embodiments disclosed herein disclose techniques whereby appropriate delays are obtained via phase shift detection circuitry and are then applied interactively by control circuitry to signal delay circuitry. Thus as is demonstrated herein, those delays which are difficult or impossible to design out can be compensated for following fabrication.
Calibration of the register is typically occurs at start-up. Additional re-calibration can be scheduled at other times to compensate for time dependent variations as, for example, caused by temperature changes.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 6118319 (2000-09-01), Yamada et al.
patent: 6329854 (2001-12-01), Lee et al.
patent: 6586979 (2003-07-01), Gomm et al.
Esch, Jr. Gerald L
Meier Peter J.
Agilent Technologie,s Inc.
Dinh Son T.
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