Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-01-17
2002-01-22
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S236000
Reexamination Certificate
active
06341097
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to methods and systems for refreshing DRAM cells. More specifically, the invention relates to such methods and systems that reduce the power consumed during the refreshing of the DRAM cells.
BACKGROUND OF THE INVENTION
DRAMs are widely used as memory storage devices in many electronic items. This widespread use is due to the facts, among others, that DRAMs are compact, inexpensive, highly reliable, and have relatively large capacities. Recently, attention has been directed to fabricating DRAMS directly on processor chips, and such DRAMs are referred to as embedded DRAMs, or eDRAMs. These eDRAMs are very well suited for use with portable devices such as portable computers, portable telephones, and other portable or handheld devices.
Embedded DRAMs, when used in hand held applications, need to minimize the current draw to aid in prolonging battery life. Since the majority of the time handheld devices are in a “standby” state, reducing the off current for the eDRAM is most important. There are three basic components of off-current: refresh current, circuit operating current and device leakage current. The present invention addresses a way to reduce or minimize the refresh current component.
Embedded DRAMs offer a “refresh-address-counter,” or RAC which allows the system to simply present a REFRESH command to the eDRAM and the appropriate wordline is refreshed, since this on chip counter keeps track of that address. One example of the RAC operation is to reset to the wordline address (to the first word line) at power-on, to increment through the entire word address space and then return to the first wordline address upon refreshing the last wordline in the eDRAM design. The “refresh rate” at which this must occur is typically in the 1-10 usec range and is a function of the technology retention time. Each time the eDRAM performs a RAC controlled refresh, current is drawn from the supply, leading to battery drain.
There are some hand held applications that utilize the full memory space during normal operation, but do no need to retain that entire space during “standby.” Since the standard RAC operation would step methodically through the entire wordline address space, power would be dissipated in refreshing some array elements whose data retention is not required.
SUMMARY OF THE INVENTION
An object of this invention is to improve methods and systems for refreshing the memory cells of DRAMs.
Another object of the present invention is to provide a partial refresh scheme for refreshing a portion of the memory cells of a DRAM.
A further object of this invention is to provide a partial refresh scheme for a DRAM that is very easy to adjust.
Another object of this invention is to reduce the standby current drawn by an eDRAM by limiting the refreshed address space to the minimum required by the system to retain data.
These and other objectives are attained with a method and system of refreshing a DRAM having a multitude of successive wordlines. The method comprises the step of starting a refresh cycle, and this starting step includes the steps of (I) counting the wordlines one at a time in succession, (ii) refreshing the wordlines counted over a first period t1, and (iii) at the end of period t1, stopping the refreshing of the wordlines, and continuing the counting of the wordlines for a period t2. The method further comprises the step of, after period t2, restarting the refresh cycle. Preferably, the restarting step includes the steps of, at the end of period t2, delaying for a period t3; and restarting the refresh cycle at the end of period t3. The method may include the further step of adjusting the length of the period t1 to change the number of wordlines refreshed during the refresh cycle. Also, preferably, during the combined periods t1 and t2, all of the wordlines are counted.
An 8 Mbit eDRAM macro can be used to illustrate the potential current savings of this invention. An 8 Mbit macro has a total of 4096 wordlines that, if the entire array space needs to retain data, with a technology cell refresh rate of 3.2 ms, requires a refresh rate of: 3.2 ms/4096=0.7 us. Assuming that each 20 ms refresh cycle draws 50 mA, then the current needed to refresh the entire array is 1.28 mA. By implementing the present invention into the RAC, this power can be reduced by the ratio: required wordline space/total wordlines pace. As an example, if ½ the wordlines with data needed to be retained, then current is halved to 0.64 mA.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.
REFERENCES:
patent: 4924381 (1990-05-01), Tokuume
patent: 5148546 (1992-09-01), Blodgett
patent: 5251176 (1993-10-01), Komatsu
patent: 6167484 (2000-12-01), Boyer et al.
Hsu Louis L.
Parent Richard Michael
Wordeman Matthew Robert
Capella Steven
International Business Machines - Corporation
Mai Son
Scully Scott Murphy & Presser
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